States encoding in multi-bit flash cells for optimizing error rate

• US 20050213393A1
• Filed: 02/22/2005
• Published: 09/29/2005
• Est. Priority Date: 03/14/2004
• Status: Abandoned Application

• Current Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Lasser, Menahem
• Application Number:
  US11/061,634
• Publication Number:
  US 20050213393A1
• Time in Patent Office: Days
• US Class Current: 365/185.330
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2^M−1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.

Claims

1. A method of storing N bits of data, comprising the steps of:

(a) providing ┌

N/M┐

cells, wherein M is at least 3; and

(b) programming each cell with up to M of the bits according to a valid physical bit ordering, and according to a logical bit ordering that is different from said physical bit ordering and that distributes error probabilities of said up to M bits more evenly than said physical bit ordering.

2. The method of claim 1, wherein said programming includes, for each cell, translating said up to M bits, as listed in said logical bit ordering, into a corresponding entry in said physical bit ordering.

3. The method of claim 1, further comprising the step of:

(c) reading said N bits from said cells.

4. The method of claim 3, wherein said reading includes, for each cell, translating an entry, in said physical bit ordering, that corresponds to a state of said each cell, into a corresponding entry in said logical bit ordering.

5. The method of claim 1, wherein said logical bit ordering substantially equalizes probability-weighted numbers of transitions of all said up to M bits.

6. The method of claim 1, wherein both said physical bit ordering and said logical bit ordering have a total number of transitions equal to 2^M−

1.

7. The method of claim 6, wherein M=3 and wherein both said physical bit ordering and said logical bit ordering have 7 transitions.

8. The method of claim 7, wherein said physical bit ordering is one of {7,6,4,5,1,0,2,3} and {7,6,4,5,1,3,2,0}.

9. The method of claim 6, wherein M=4 and wherein both said physical bit ordering and said logical bit ordering have 15 transitions.

10. The method of claim 6, wherein said logical bit ordering is evenly distributed.

11. The method of claim 10, wherein M=4, wherein a number of transitions of any bit of said logical bit ordering is selected from the group consisting of 3 and 4.

12. The method of claim 1, wherein said physical bit ordering is nonserial.

13. A memory device comprising:

(a) a memory that includes K cells; and

(b) a controller operative to store N bits of data in said cells by programming each said cell with up to M=┌

N/K┐

of said bits according to a valid physical bit ordering, and according to a logical bit ordering that is different from said physical bit ordering and that distributes error probabilities of said up to M bits more evenly than said physical bit ordering, wherein M is at least 3.

14. The memory device of claim 13, wherein said controller includes a mechanism for translating between said physical bit ordering and said logical bit ordering.

15. The memory device of claim 14, wherein said mechanism effects said translating by executing software.

16. The memory device of claim 14, wherein said controller includes dedicated hardware for effecting said translating.

17. The memory device of claim 13, wherein said memory includes dedicated hardware for translating between said physical bit ordering and said logical bit ordering.

18. The memory device of claim 13, wherein said memory is a flash memory.

19. The memory device of claim 13, wherein said physical bit ordering is nonserial.

20. A system for storing data, comprising:

(a) a memory device that includes a memory, said memory including K cells;

(b) a host of said memory device, for providing N bits of data to store; and

(c) a mechanism for translating, for each said cell, up to M=┌

N/K┐

of said bits, as listed in a logical bit ordering, into a corresponding entry in a valid physical bit ordering that is different from said logical bit ordering, wherein M is at least 3, said each cell then being programmed according to said entry in said physical bit ordering, said logical bit ordering distributing error probabilities of said up to M bits more evenly than said physical bit ordering.

21. The system of claim 20, wherein said mechanism effects said translating by executing software.

22. The system of claim 21, wherein said mechanism is included in said host.

23. The system of claim 21, wherein said mechanism is included in a controller of said memory, said controller being included in said memory device.

24. The system of claim 20, wherein said mechanism includes dedicated hardware for effecting said translating.

25. The system of claim 24, wherein said mechanism is included in said memory.

26. The system of claim 24, wherein said mechanism is included in a controller of said memory, said controller being included in said memory device.

27. The system of claim 20, wherein said memory is a flash memory.

28. The system of claim 20, wherein said physical bit ordering is nonserial.

29. A method of storing N bits of data, comprising the steps of:

(a) providing ┌

N/M┐

cells, wherein M is at least 3; and

(b) programming each cell with up to M of the bits according to a valid physical bit ordering, and according to an evenly distributed logical bit ordering that is different from said physical bit ordering.

30. A memory device comprising:

(a) a memory that includes K cells; and

(b) a controller operative to store N bits of data in said cells by programming each said cell with up to M==┌

N/K┐

of said bits according to a valid physical bit ordering, and according to an evenly distributed logical bit ordering, wherein M is at least 3.

31. A system for storing data, comprising:

(a) a memory device that includes a memory, said memory including K cells;

(b) a host of said memory device, for providing N bits of data to store; and

(c) a mechanism for translating, for each said cell, up to M=┌

N/K┐

of said bits, as listed in an evenly distributed logical bit ordering, into a corresponding entry in a valid physical bit ordering that is different from said logical bit ordering, wherein M is at least 3, said each cell then being programmed according to said entry in said physical bit ordering.

32. A method of storing N bits of data, comprising the steps of:

(a) providing ┌

N/M┐

cells, wherein M is at least 3; and

(b) programming each cell with up to M of the bits according to a valid, nonserial bit ordering that distributes error probabilities of all said up to M bits substantially evenly.

33. A memory device comprising:

(a) a memory that includes K cells; and

(b) a controller operative to store N bits of data in said cells by programming each said cell with up to M=┌

N/K┐

of said bits according to a valid, nonserial bit ordering that distributes error probabilities of all said up to M bits substantially evenly, wherein M is at least 3.

34. A method of of storing N bits of data, comprising the steps of:

(a) providing ┌

N/M┐

cells, wherein M is at least 3; and

(b) programming each cell with up to M of the bits according to a valid, nonserial, error-rate-optimal bit ordering.

35. The method of claim 34, wherein a total number of transitions in said bit ordering is a minimum said number of transitions.

36. The method of claim 34, wherein said bit ordering has a total number of transitions equal to 2^M−

1.

37. The method of claim 36, wherein M=3 and wherein said bit ordering has seven said transitions.

38. The method of claim 37, wherein said bit ordering is selected from the group consisting of {7,6,4,5,1,0,2,3} and {7,6,4,5,1,3,2,0}.

39. The method of claim 36, wherein M=4 and wherein said bit ordering has fifteen said transitions.

40. The method of claim 34, wherein said bit ordering is evenly distributed.

41. The method of claim 40, wherien M=4 and wherein each bit of said bit ordering has at least three transitions and at most four transitions.

42. A memory device comprising:

(a) a memory that includes K cells; and

(b) a controller operative to store N bits of data in said cells by programming each cell with up to M=┌

N/K┐

of said bits according to a valid, nonserial, error-rate-optimal bit ordering, wherein M is at least 3.