Electrical fuse control of memory slowdown

• US 20050213411A1
• Filed: 05/03/2005
• Published: 09/29/2005
• Est. Priority Date: 07/30/2003
• Status: Active Grant

• Current Assignee: Bryan Sheffield, Duy-Loan Le, Joel J. Graber, Manjeri Krishnan, Sanjive Agarwala
• Original Assignee: Bryan Sheffield, Duy-Loan Le, Joel J. Graber, Manjeri Krishnan, Sanjive Agarwala
• Inventors: Graber, Joel J., Agarwala, Sanjive, Krishnan, Manjeri, Sheffield, Bryan, Le, Duy-Loan
• Granted Patent: US 7,095,671 B2
• Time in Patent Office: Days
• US Class Current: 365/225.700
• CPC Class Codes: G11C 29/027 in fuses
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing

Abstract

Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.

Claims

1. to 15. (canceled)

16. An integrated circuit comprising:

a plurality of write once bits including at least one read timing write once bit and at least one write timing write once bit;

a logic circuit;

a read/write memory connected to said write once bits and said logic circuit, said read/write memory operable to read data from memory locations specified by said logic circuit and write data to memory locations specified by said logic circuit, said read/write memory including

a read timing circuit selecting one of a plurality of intervals of time from a start of read operations until sampling of read data dependent upon said at least one read timing write once bit, and

a write timing circuit selecting one of a plurality of intervals of time of application of write data to said corresponding memory locations dependent upon said at least one write timing write once bit.

17. The integrated circuit of claim 16, wherein:

said logic circuit includes a programmable data processor.

18. The integrated circuit of claim 16, further comprising:

a plurality of data bit latches, one data bit latch corresponding to each of said write once bits;

wherein said reading timing circuit is responsive to said data bit latches corresponding to said at least one read timing write one bit in a test mode; and

wherein said write timing circuit is responsive to said data bit latches corresponding to said at least one write timing write one bit in a test mode.

19. An integrated circuit comprising:

a plurality of write once bits including at least one read timing write once bit;

a logic circuit;

a read accessible memory connected to said write once bits and said logic circuit, said read accessible memory operable to read data from memory locations specified by said logic circuit, said read accessible write memory including

a read timing circuit selecting one of a plurality of intervals of time from a start of read operations until sampling of read data dependent upon said at least one read timing write once bit.

20. The integrated circuit of claim 19, wherein:

said logic circuit includes a programmable data processor.

21. The integrated circuit of claim 19, further comprising:

a plurality of data bit latches, one data bit latch corresponding to each of said write once bits;

wherein said reading timing circuit is responsive to said data bit latches corresponding to said at least one read timing write one bit in a test mode.

22. An integrated circuit comprising:

a plurality of write once bits including at least one write timing write once bit;

a logic circuit;

a write accessible memory connected to said write once bits and said logic circuit, said write accessible memory operable to write data to memory locations specified by said logic circuit, said write accessible memory including

a write timing circuit selecting one of a plurality of intervals of time of application of write data to said corresponding memory locations dependent upon said at least one write timing write once bit.

23. The integrated circuit of claim 22, wherein:

said logic circuit includes a programmable data processor.

24. The integrated circuit of claim 22, further comprising:

a plurality of data bit latches, one data bit latch corresponding to each of said write once bits;

wherein said write timing circuit is responsive to said data bit latches corresponding to said at least one write timing write one bit in a test mode.