Method and system for synchronizing communications links in a hub-based memory system
First Claim
1. A method of synchronizing communications links in a memory system including a system controller and a plurality of memory hubs coupled in series, with pairs of downstream and upstream links being coupled between adjacent modules and the controller, and the method comprising:
- synchronizing an upstream and downstream link coupled to the controller;
sequentially synchronizing downstream links starting with the downstream link coupled between the controller and the first hub;
sequentially synchronizing upstream links starting with the upstream link coupled between the last memory hub and the next upstream hub;
providing an indication to the controller when the upstream link between the first and second hubs has been synchronized;
sequentially enabling downstream links to process functional commands;
sequentially enabling upstream links to process functional commands, and providing an indication to the controller that all links have been enabled.
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Accused Products
Abstract
A method is disclosed for synchronizing communications links in a memory hub system. The system includes a system controller and a plurality of memory hubs coupled in series, with pairs of downstream and upstream links being coupled between adjacent modules and the controller. The method includes synchronizing each upstream and downstream link. In a clockwise order starting with the downstream link coupled between the controller and the first memory module, the next adjacent clockwise link is signaled that the prior clockwise link has been synchronized. The method detects through the upstream link coupled between the controller and the first memory module when all links have been synchronized. In a clockwise order starting with the downstream link coupled between the controller and the first memory module, each link is enabled. The method detects through the upstream link coupled between the controller and first memory module when all links have been enabled.
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Citations
44 Claims
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1. A method of synchronizing communications links in a memory system including a system controller and a plurality of memory hubs coupled in series, with pairs of downstream and upstream links being coupled between adjacent modules and the controller, and the method comprising:
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synchronizing an upstream and downstream link coupled to the controller;
sequentially synchronizing downstream links starting with the downstream link coupled between the controller and the first hub;
sequentially synchronizing upstream links starting with the upstream link coupled between the last memory hub and the next upstream hub;
providing an indication to the controller when the upstream link between the first and second hubs has been synchronized;
sequentially enabling downstream links to process functional commands;
sequentially enabling upstream links to process functional commands, and providing an indication to the controller that all links have been enabled. - View Dependent Claims (2, 3, 4, 5)
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6. A method of synchronizing communications links in a memory hub system including a system controller and a plurality of memory hubs coupled in series, with pairs of downstream and upstream links being coupled between adjacent modules and the controller, and the method comprising:
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synchronizing each upstream and downstream link;
in a clockwise order starting with the downstream link coupled between the controller and the first memory module, signaling to the next adjacent clockwise link that the prior clockwise link has been synchronized;
detecting through the upstream link coupled between the controller and the first memory module when all links have been synchronized;
in a clockwise order starting with the downstream link coupled between the controller and the first memory module, enabling each link; and
detecting through the upstream link coupled between the controller and the first memory module when all links have been enabled. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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14. A memory hub, comprising:
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a downstream reception interface operable in an initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the interface in the normal mode of operation;
a downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the downstream reception interface, and operable in the enablement mode responsive to the enablement signal from the downstream reception interface to provide the enablement command on the output and to place the interface into the normal mode of operation;
an upstream reception interface operable in the initialization mode to adjust a phase of the generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the interface into the normal mode of operation; and
an upstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the upstream reception interface, and operable in the enablement mode responsive to the enablement signal from the upstream reception interface to provide the enablement command on the output and to place the interface into the normal mode of operation. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21)
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22. A memory module, comprising:
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a plurality of memory devices; and
a memory hub, comprising;
a downstream reception interface operable in an initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the interface in the normal mode of operation;
a downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the downstream reception interface, and operable in the enablement mode responsive to the enablement signal from the downstream reception interface to provide the enablement command on the output and to place the interface into the normal mode of operation;
an upstream reception interface operable in the initialization mode to adjust a phase of the generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the interface into the normal mode of operation;
an upstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the upstream reception interface, and operable in the enablement mode responsive to the enablement signal from the upstream reception interface to provide the enablement command on the output and to place the interface into the normal mode of operation; and
local hub circuitry coupled to the interfaces and to the memory devices. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
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30. A memory system, comprising:
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a plurality of memory modules coupled in series, each module being coupled to adjacent modules through respective downstream and upstream high-speed communications links, each memory module comprising;
a plurality of memory devices; and
a memory hub, comprising;
a downstream reception interface operable in an initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the interface in the normal mode of operation;
a downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the downstream reception interface, and operable in the enablement mode responsive to the enablement signal from the downstream reception interface to provide the enablement command on the output and to place the interface into the normal mode of operation;
an upstream reception interface operable in the initialization mode to adjust a phase of the generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the interface into the normal mode of operation;
an upstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the upstream reception interface, and operable in the enablement mode responsive to the enablement signal from the upstream reception interface to provide the enablement command on the output and to place the interface into the normal mode of operation; and
local hub circuitry coupled to the interfaces and to the memory devices; and
a system controller coupled to a first one of the memory modules through respective downstream and upstream high-speed communications links. - View Dependent Claims (31, 32, 33, 34, 35, 36, 37, 38)
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39. A computer system, comprising:
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a processor;
a system controller coupled to the processor through respective downstream and upstream high-speed communications links;
a memory system, comprising;
a plurality of memory modules coupled in series, each module being coupled to adjacent modules through respective downstream and upstream high-speed communications links, and a first one of the modules being coupled to the processor through respective downstream and upstream high-speed communications links, each memory module comprising;
a plurality of memory devices; and
a memory hub, comprising;
a downstream reception interface operable in an initialization mode to adjust a phase of a generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the interface in the normal mode of operation;
a downstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the downstream reception interface, and operable in the enablement mode responsive to the enablement signal from the downstream reception interface to provide the enablement command on the output and to place the interface into the normal mode of operation;
an upstream reception interface operable in the initialization mode to adjust a phase of the generated receive clock signal relative to applied test data signals and to generate an inversion signal once a final phase of the generated receive clock signal is determined, and operable in an enablement mode responsive to receiving an enablement command to generate an enablement signal and to place the interface into the normal mode of operation;
an upstream transmission interface operable in the initialization mode to apply test data signals on an output and operable to adjust the value of the test data signals responsive to the inversion signal from the upstream reception interface, and operable in the enablement mode responsive to the enablement signal from the upstream reception interface to provide the enablement command on the output and to place the interface into the normal mode of operation; and
local hub circuitry coupled to the interfaces and to the memory devices. - View Dependent Claims (40, 41, 42, 43, 44)
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Specification