Electric device, matrix device, electro-optical display device, and semiconductor memory having thin-film transistors

• US 20050214990A1
• Filed: 05/31/2005
• Published: 09/29/2005
• Est. Priority Date: 05/29/1992
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Takemura, Yasuhiko, Yamazaki, Shunpei
• Granted Patent: US 7,223,996 B2
• Time in Patent Office: Days
• US Class Current: 438/155
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

A circuit adapted to dynamically activate an electro-optical display device is constructed from a thin-film gate-insulated semiconductor device. This device comprises PMOS TFTs producing only a small amount of leakage current. Besides the dynamic circuit, a CMOS circuit comprising both NMOS and PMOS thin-film transistors is constructed to drive the dynamic circuit.

Claims

1. A method of manufacturing a semiconductor device comprising at least two p-channel thin film transistors,

said method comprising the steps of:

forming a semiconductor island over a substrate;

forming a gate electrode adjacent to the semiconductor island with a gate insulating film therebetween;

forming a source region, a drain region and a channel region formed between the source and drain regions,

wherein the two p-channel thin film transistors are connected in series.