Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same

• US 20050215012A1
• Filed: 05/25/2005
• Published: 09/29/2005
• Est. Priority Date: 05/25/1999
• Status: Active Grant

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K., Grabowski, Wayne B.
• Granted Patent: US 7,276,411 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

Claims

1. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a trench in said semiconductor material, said trench extending from a surface of said semiconductor material into said semiconductor material;

depositing a polysilicon layer, said polysilicon layer filling said trench and overflowing said surface of said semiconductor material; and

removing a sufficient amount of said polysilicon layer such that a surface of said polysilicon layer is substantially coplanar with said surface of said semiconductor material, said removing comprising chemical-mechanical polishing.

2. The process of claim 1 comprising performing the following after forming said trench but before depositing said polysilicon layer:

directionally depositing a thick oxide layer on said semiconductor material, said thick oxide layer depositing preferentially on horizontal surfaces so as to form a first thick portion in a bottom of said trench and a thin portion on a sidewall of said trench.

3. The process of claim 2 comprising:

forming a second oxide layer over said surfaces of said polysilicon layer and said semiconductor material;

forming a mask layer over said second oxide layer;

etching said second oxide layer through an opening in said mask layer so as to leave a portion of said second oxide layer overlying said surface of said polysilicon layer and a portion of said surface of said semiconductor material.

4. The process of claim 2 comprising the following after removing a sufficient amount of said polysilicon layer:

annealing said polysilicon layer to form an oxide cap.

5. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a trench in said semiconductor material, said trench extending from a surface of said semiconductor material into said semiconductor material;

directionally depositing a thick oxide layer on said semiconductor material, said oxide layer depositing preferentially on horizontal surfaces so as to form a first thick portion in a bottom of said trench and a second thick portion over said surface of said semiconductor material, and a thin portion on a sidewall of said trench;

removing said thin portion of said thick oxide layer from said sidewall of said trench;

growing a gate oxide layer on said sidewall of said trench

depositing a first polysilicon layer, said first polysilicon layer filling said trench and overflowing said second thick portion of said thick oxide layer;

etching a sufficient amount of said first polysilicon layer such that a surface of said polysilicon layer is located inside said trench;

depositing a second polysilicon layer; and

etching a sufficient amount of said second polysilicon layer such that a surface of said second polysilicon layer is located adjacent said second thick portion of said thick oxide layer.