Trench semiconductor device having gate oxide layer with multiple thicknesses and processes of fabricating the same

• US 20050215027A1
• Filed: 05/25/2005
• Published: 09/29/2005
• Est. Priority Date: 05/25/1999
• Status: Active Grant

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K., Grabowski, Wayne B.
• Granted Patent: US 7,282,412 B2
• Time in Patent Office: Days
• US Class Current: 438/424
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

Claims

1. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a trench in said semiconductor material, said trench extending from a surface of said semiconductor material into said semiconductor material;

thermally growing an oxide lining on the sidewalls and bottom of said trench;

directionally depositing a thick oxide layer, said oxide layer depositing preferentially on horizontal surfaces so as to form a first thick portion over said oxide lining at a bottom of said trench and a thin portion on said oxide lining on said sidewall of said trench.

2. The process of claim 1 comprising thermally growing and removing a sacrificial oxide layer on the sidewalls of said trench before thermally growing said oxide lining.

3. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a trench in said semiconductor material, said trench extending from a surface of said semiconductor material into said semiconductor material;

directionally depositing a thick oxide layer on said semiconductor material, said oxide layer depositing preferentially on horizontal surfaces so as to form a thick portion in a bottom of said trench and a thin portion on a sidewall of said trench;

depositing a photoresist layer;

removing all of said photoresist layer except for a remaining portion of said photoresist layer that overlies said thick portion of said thick oxide layer; and

removing said thin portion of said thick oxide layer from said sidewall of said trench.

4. The process of claim 3 comprising removing said remaining portion of said photoresist layer.

5. The process of claim 4 comprising growing a gate oxide layer on said sidewall of said trench.

6. The process of claim 5 comprising forming a polysilicon layer in said trench.

7. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a trench in said semiconductor material, said trench extending from a surface of said semiconductor material into said semiconductor material;

directionally depositing a thick oxide layer on said semiconductor material, said oxide layer depositing preferentially on horizontal surfaces so as to form a thick portion in a bottom of said trench and a thin portion on a sidewall of said trench;

depositing a polysilicon layer;

removing all of said polysilicon layer except for a remaining portion of said polysilicon layer that overlies said thick portion of said thick oxide layer;

oxidizing said remaining portion of said polysilicon layer; and

removing said thin portion of said thick oxide layer from said sidewall of said trench.

8. The process of claim 7 wherein oxidizing said remaining portion of said polysilicon layer comprises heating said remaining portion of said polysilicon layer to a temperature in the range of 700 to 950°

C.

9. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a mask layer on a surface of said semiconductor material;

forming a first opening in said mask layer, said first opening exposing an exposed are of said surface of said semiconductor material;

depositing a second layer on said mask layer and on said exposed area;

anisotropically etching said second layer so as to leave sidewall spacers on edges of said mask layer facing said first opening, the separation between said sidewall spacers forming a second opening narrower than said first opening;

forming a trench in said semiconductor material by etching said semiconductor material through said second opening;

forming a gate oxide layer on a sidewall of said trench;

directionally depositing a thick oxide layer, said thick oxide layer depositing preferentially on horizontal surfaces so as to form a first thick portion in a bottom of said trench and a second thick portion on said second layer; and

forming a polysilicon gate in said trench.

10. The process of claim 9 wherein forming a polysilicon gate comprises:

depositing a polysilicon layer in said trench and over a surface of said second thick portion of said oxide layer; and

etching said polysilicon layer until a surface of said polysilicon layer is adjacent said sidewall spacers.

11. The process of claim 10 comprising removing said second thick portion of said thick oxide layer.

12. The process of claim 9 wherein forming a mask layer comprises:

forming a first oxide sublayer on said surface of said semiconductor material;

depositing a nitride sublayer on said first oxide sublayer; and

depositing a second oxide sublayer on said nitride sublayer.

13. The process of claim 12 comprising removing said second oxide sublayer before forming said trench, leaving said sidewall spacer on edges of said first oxide sublayer and said nitride sublayer.