Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods

• US 20050218395A1
• Filed: 03/15/2005
• Published: 10/06/2005
• Est. Priority Date: 03/16/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Won, Lee, Jong-Wook, Kim, Sung-Min, Choi, Si-Young, Jung, In-Soo, Son, Yong-Hoon, Yeo, Kyoung-Hwan, Lee, Young-Eun, Lee, Byeong-Chan
• Granted Patent: US 7,429,504 B2
• Time in Patent Office: Days
• US Class Current: 257/12
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.

Claims

1. A heterogeneous semiconductor substrate, comprising:

a first Group IV semiconductor layer;

a second Group IV semiconductor pattern that includes a plurality of individual elements on the first Group IV semiconductor layer; and

a third Group IV semiconductor layer having a planarized upper surface on the second Group IV semiconductor pattern and on a plurality of exposed portions of the first Group IV semiconductor layer;

wherein the planarized upper surface of the third Group IV semiconductor layer comprises the upper surface of the heterogeneous semiconductor substrate.

2. The heterogeneous semiconductor substrate of claim 1, wherein the first Group IV semiconductor layer comprises a single crystalline silicon substrate, the second Group IV semiconductor pattern comprises a silicon-germanium epitaxial pattern, and the third Group IV semiconductor layer comprises a silicon epitaxial layer.

3. The heterogeneous semiconductor substrate of claim 1, wherein the first and third Group IV semiconductor layers comprise a first material and the second Group IV semiconductor pattern comprises a second material that has different electrical and chemical properties than the first material.

4. The heterogeneous semiconductor substrate of claim 1, wherein the third Group IV semiconductor layer is directly on the first Group IV semiconductor layer in exposed areas between the individual elements of the second Group IV semiconductor pattern.

5. A method of forming a heterogeneous semiconductor substrate comprising:

forming a second Group IV semiconductor pattern having a planar upper surface on a planar upper surface of a first Group IV semiconductor layer; and

forming a third Group IV semiconductor layer having a planar upper surface on the planar upper surface of the second Group IV semiconductor pattern and on the planar upper surfaces of a plurality of exposed portions of the first Group IV semiconductor layer to provide the heterogeneous semiconductor substrate.

6. The method of claim 5, wherein forming the third Group IV semiconductor layer having the planar upper surface comprises:

growing a primary Group IV epitaxial layer on the planar upper surface of the second Group IV semiconductor pattern and on the planar upper surfaces of the plurality of exposed portions of the first Group IV semiconductor layer at a first temperature such that a surface movement of the second Group IV semiconductor pattern does not occur; and

forming a secondary Group IV epitaxial layer having a planar upper surface at a second temperature such that a surface movement of the primary Group IV epitaxial layer occurs.

7. The method of claim 6, wherein the first temperature is between about 300°

C. and about 800°

C., and the second temperature is between about 800°

C. and about 1200°

C.

8. The method of claim 5, wherein forming the third Group IV semiconductor layer having the planar upper surface comprises:

growing a Group IV epitaxial layer on the planar upper surface of the second Group IV semiconductor pattern and on the planar upper surfaces of the plurality of exposed portions of the first Group IV semiconductor layer at a first temperature such that a surface movement of the second Group IV semiconductor pattern does not occur; and

planarizing the upper surface of the Group IV epitaxial layer by performing a thermal process at a second temperature such that a surface movement of the Group IV epitaxial layer occurs.

9. The method of claim 8, wherein the first temperature is between about 300°

C. and about 800°

C., the second temperature is between about 600°

C. and about 1200°

C.; and

wherein the thermal process is performed in a hydrogen gas ambient.

10. The method of claim 8, wherein the first temperature is between about 300°

C. and about 800°

C., the second temperature is between about 900°

C. and 1200°

C.; and

wherein the thermal process is performed in an argon gas ambient.

11. The method of claim 5, wherein the first Group IV semiconductor layer is a single crystalline silicon substrate, and

wherein forming the second Group IV semiconductor pattern comprises growing a silicon-germanium epitaxial layer on the single crystalline silicon substrate and patterning the silicon-germanium expitaxial layer, and

wherein forming the third Group IV semiconductor layer comprises growing a silicon epitaxial layer on surfaces of the single crystalline silicon substrate and the silicon-germanium epitaxial layer.

12. The method of claim 11, wherein forming the third Group IV semiconductor layer further comprises:

growing the silicon epitaxial layer at a first temperature such that a surface movement of the patterned silicon-germanium epitaxial layer does not occur; and

forming a secondary silicon epitaxial layer having a planar upper surface on the silicon epitaxial layer at a second temperature that is higher then the first temperature such that a surface movement of the silicon epitaxial layer occurs.

13. The method of claim 12, wherein the first temperature is between about 300°

C. and about 800°

C., and the second temperature is between about 800°

C. and about 1200°

C.

14. The method of claim 11, wherein forming the third Group IV semiconductor layer further comprises:

growing the silicon epitaxial layer at a first temperature such that a surface movement of the patterned silicon-germanium epitaxial layer does not occur; and

planarizing the upper surface of the silicon epitaxial layer by performing a thermal process at a second temperature that is higher then the first temperature such that a surface movement of the silicon epitaxial layer occurs.

15. The method of claim 14, wherein the first temperature is between about 300°

C. and about 800°

C., the second temperature is between about 600°

C. and about 1200°

C.

16. A method of forming an integrated circuit, comprising:

forming a second Group IV semiconductor pattern on a first Group IV semiconductor layer; and

forming a third Group IV semiconductor layer on the second Group IV semiconductor pattern and on a plurality of exposed portions of the first Group IV semiconductor layer to provide a heterogeneous substrate;

forming at least one semiconductor device on the heterogeneous substrate.

17. The method of claim 16, further comprising, prior to forming the at least one semiconductor device, selectively removing at least portions of the second Group IV semiconductor pattern to provide a plurality of voids within the heterogeneous substrate.

18. The method of claim 17, further comprising at least partially filling at least some of the plurality of voids with an insulating material.

19. The method of claim 17, wherein forming the third Group IV semiconductor layer comprises:

growing a primary Group IV epitaxial layer on the second Group IV semiconductor pattern and on the plurality of exposed portions of the first Group IV semiconductor layer at a first temperature such that a surface movement of the second Group IV semiconductor pattern does not occur; and

forming a secondary Group IV epitaxial layer having a planar upper surface at a second temperature that is higher then the first temperature such that a surface movement of the primary Group IV epitaxial layer occurs.

20. The method of claim 17, wherein forming the third Group IV semiconductor layer comprises:

growing a Group IV epitaxial layer on the second Group IV semiconductor pattern and on the plurality of exposed portions of the first Group IV semiconductor layer at a first temperature such that a surface movement of the second Group IV semiconductor pattern does not occur; and

planarizing the upper surface of the Group IV epitaxial layer by performing a thermal process at a second temperature that is higher then the first temperature such that a surface movement of the Group IV epitaxial layer occurs.

21. The method of claim 18, wherein the first Group IV semiconductor layer is a single crystalline silicon substrate, and

wherein forming the second Group IV semiconductor pattern comprises growing a silicon-germanium epitaxial layer on the single crystalline silicon substrate and patterning the silicon-germanium expitaxial layer, and

wherein forming the third Group IV semiconductor layer comprises growing a silicon epitaxial layer directly on surfaces of the single crystalline silicon substrate and on the silicon-germanium epitaxial layer.

22. The method of claim 19, wherein forming the at least one semiconductor device comprises forming a field effect transistor such that a source region overlaps a first of the plurality of voids with an insulating material and a drain region of the field effect transistor overlaps a second of the plurality of voids with an insulating material.

23. The method of claim 22, wherein the first and second of the plurality of voids with an insulating material are used to control the depth of the source region and the depth of the drain region, respectively.