Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
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Abstract
A method of a bulk tri-gate transistor having stained enhanced mobility and its method of fabrication. The present invention is a nonplanar transistor having a strained enhanced mobility and its method of fabrication. The transistor has a semiconductor body formed on a semiconductor substrate wherein the semiconductor body has a top surface on laterally opposite sidewalls. A semiconductor capping layer is formed on the top surface and on the sidewalls of the semiconductor body. A gate dielectric layer is formed on the semiconductor capping layer on the top surface of a semiconductor body and is formed on the capping layer on the sidewalls of the semiconductor body. A gate electrode having a pair of laterally opposite sidewalls is formed on and around the gate dielectric layer. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.
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Citations
42 Claims
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1-19. -19. (canceled)
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20. A method of forming a semiconductor device comprising:
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forming a pair of isolation regions in a semiconductor substrate, said pair of isolation regions defining an active substrate region in said semiconductor substrate therebetween, said isolation region extending above said substrate;
forming a semiconductor film on said active region of said semiconductor substrate between said pair of isolation regions;
etching back said isolation regions to form a semiconductor body from said semiconductor film wherein said semiconductor body has a top surface and a pair of laterally opposite sidewalls;
forming a semiconductor capping layer on said top surface and said sidewalls of said semiconductor body;
forming a gate dielectric layer over said capping layer formed on said sidewalls of said top surface of said semiconductor body;
forming a gate electrode having a pair of laterally opposite sidewalls on and around said gate dielectric layer; and
forming a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A method of forming a semiconductor device comprising:
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forming a pair of spaced apart isolation regions in a semiconductor substrate, said spaced apart isolation regions defining an active substrate area in said substrate wherein said isolation regions extend above said active substrate area;
forming a semiconductor film on said active area of said substrate between said isolation regions;
forming a first capping layer on said top surface of said semiconductor film between said isolation regions;
etching back said isolation regions to form a semiconductor body having a top surface with said first capping layer and a pair of laterally opposite sidewalls;
forming a second capping layer on said first capping layer on the top surface of said semiconductor body and on said sidewalls of said semiconductor body;
forming a gate dielectric layer on said second capping layer on said first capping layer on said semiconductor body and on said second capping layer on said sidewalls of said semiconductor body;
forming a gate electrode having a pair of laterally opposite sidewalls on and around said gate dielectric layer; and
forming a pair of source/drain regions in said semiconductor body on opposite sides of said gate electrode. - View Dependent Claims (33, 34, 35, 36, 37)
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38. A method of forming a semiconductor device comprising:
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forming a first semiconductor body and a second semiconductor body on a substrate, said first and said second semiconductor bodies each having a top surface and a pair of laterally opposite sidewalls, said first semiconductor body and said second semiconductor body separated by a distance;
forming a semiconductor capping layer on said sidewalls and said top surface of said first and said second semiconductor bodies;
forming a gate dielectric layer on said top surface and said sidewalls of said first and said second semiconductor bodies; and
forming a gate electrode on said gate dielectric layer on said top surface of said first and second semiconductor bodies and adjacent to said gate dielectric layer on said sidewalls of said first and second semiconductor bodies. - View Dependent Claims (39, 40, 41, 42)
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Specification