Process of fabricating termination region for trench MIS device
First Claim
1. A process of fabricating a termination region for a trench MIS device comprising:
- providing a semiconductor wafer, said wafer comprising a first layer of a first conductivity type and a second layer of a second conductivity type overlying said first layer;
forming a first trench in said wafer, said first trench coinciding with a scribe line bordering a die of said wafer, a bottom of said first trench being located in said second layer;
introducing a dopant of said first conductivity type through a bottom of said first trench to form a region of said first conductivity type extending from said bottom of said first trench to said first layer;
forming an insulating layer in said first trench and over a surface of said layer of second conductivity type;
forming a termination metal layer over said insulating layer in said first trench and over said surface of said layer of second conductivity type;
etching an opening in said metal layer at a bottom of said first trench, said scribe line intersecting said opening; and
sawing said wafer at said scribe line.
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Accused Products
Abstract
A trench MIS device is formed in a semiconductor die that contains a P-epitaxial layer that overlies an N+ substrate and an N-epitaxial layer. In one embodiment, the device includes a drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. A termination region of the die includes a half-trench at an edge of the die and an N-type region that extends from a bottom of the half-trench to the substrate. An insulating layer and an overlying metal layer extend from the surface of the epitaxial layer into the half-trench. Preferably, the elements of the termination region are formed during the same process steps that are used to form the active elements of the device.
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Citations
12 Claims
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1. A process of fabricating a termination region for a trench MIS device comprising:
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providing a semiconductor wafer, said wafer comprising a first layer of a first conductivity type and a second layer of a second conductivity type overlying said first layer;
forming a first trench in said wafer, said first trench coinciding with a scribe line bordering a die of said wafer, a bottom of said first trench being located in said second layer;
introducing a dopant of said first conductivity type through a bottom of said first trench to form a region of said first conductivity type extending from said bottom of said first trench to said first layer;
forming an insulating layer in said first trench and over a surface of said layer of second conductivity type;
forming a termination metal layer over said insulating layer in said first trench and over said surface of said layer of second conductivity type;
etching an opening in said metal layer at a bottom of said first trench, said scribe line intersecting said opening; and
sawing said wafer at said scribe line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification