Semiconductor substrate with interconnections and embedded circuit elements

• US 20050218509A1
• Filed: 03/31/2004
• Published: 10/06/2005
• Est. Priority Date: 03/31/2004
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Rao, Valluri R., Kipnis, Issy
• Granted Patent: US 7,312,505 B2
• Time in Patent Office: Days
• US Class Current: 257/723
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19107 off-chip wires
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor substrate integrated with interconnections and circuit components. A silicon backplane is processed with silicon processing to provide electrical connectivity for circuit elements. In one embodiment functional circuit elements, e.g., MEMS, switches, filters, are integrated on the silicon backplane. In one embodiment the function circuit elements are monolithically processed into the silicon backplane. In one embodiment the silicon backplane includes interconnections for integrated circuits on different substrates to be bonded to the silicon backplane.

Claims

1. An interconnect apparatus comprising:

a silicon substrate;

contact pads processed on the silicon substrate to connect to an integrated circuit (IC) die;

interconnections selectively interconnecting the contact pads, the interconnections processed on the silicon substrate; and

circuit elements processed on the silicon substrate with the same processing as the contact pads and the interconnections to interoperate with the IC die.

2. An interconnect apparatus according to claim 1, wherein the circuit elements comprise a micro electromechanical system (MEMS) device.

3. An interconnect apparatus according to claim 2, wherein the MEMS device further includes a microfluidic system.

4. An interconnect apparatus according to claim 2, wherein the MEMS device further includes an actuation circuit device.

5. An interconnect apparatus according to claim 1, wherein the circuit elements comprise a sensor circuit.

6. An interconnect apparatus according to claim 1, wherein the silicon substrate comprises a high-resistivity silicon substrate.

7. An interconnect apparatus according to claim 6, wherein the circuit elements comprise optical circuit components.

8. An interconnect apparatus according to claim 1, wherein the circuit elements comprise an active circuit element.

9. An interconnect apparatus according to claim 1, further comprising a cap processed onto the silicon substrate to hermetically isolate circuit elements on the silicon substrate.

10. An interconnect apparatus according to claim 9, wherein the cap comprises a cap of silicon-based material.

11. An interconnect apparatus according to claim 9, further comprising interconnect vias manufactured in the cap to provide electrical connectivity to contact pads on the silicon substrate.

12. A method comprising:

integrating interconnections and passive circuit elements into a silicon backplane with processing steps of a first precision level; and

integrating on the interconnections of the silicon backplane an integrated circuit (IC) produced on a separate silicon substrate with a second precision level of processing, the IC to interconnect with the passive circuit elements, the second precision level being more precise than the first precision level.

13. A method according to claim 12, wherein integrating interconnections and passive elements into the silicon backplane comprises integrating into high-resistivity silicon.

14. A method according to claim 12, further comprising integrating a micro electro-mechanical system (MEMS) device into the silicon backplane with the processing steps of the first precision level.

15. A method according to claim 14, wherein the MEMS device further comprises a film bulk acoustic resonator (FBAR) device.

16. A method according to claim 12, wherein integrating on the interconnections of the silicon backplane the IC comprises flip-chip bonding the IC to the silicon backplane.

17. A method according to claim 12, further comprising integrating multiple ICs on the silicon backplane, each of the ICs being silicon-based ICs.

18. A method according to claim 17, wherein integrating the ICs on the silicon backplane comprises creating an all silicon-based radio front-end module IC.

19. An integrated circuit chip having a circuit element on a substrate created with a first lithographic processing interconnected on a high-resistivity silicon interconnect substrate having functional circuit elements embedded in the interconnect substrate, created by the process of:

processing contact pads and electrical traces on the silicon substrate with a second lithographic processing to interconnect the circuit elements;

processing the circuit elements on the interconnection substrate with the second lithographic processing; and

interconnecting the circuit element of the first lithographic processing on the separate substrate to contact pads on the interconnection substrate.

20. An integrated circuit chip according to claim 19, wherein the silicon interconnect substrate further includes a micro electromechanical system (MEMS) device.

21. An integrated circuit chip according to claim 19, wherein the circuit elements comprise an active circuit element.

22. An integrated circuit chip according to claim 19, wherein the circuit elements on separate substrates comprise circuit elements all on silicon substrates.

23. An integrated circuit chip according to claim 19, wherein the silicon interconnect substrate further comprises a silicon lid to hermetically seal functional circuit elements.

24. An integrated circuit chip according to claim 23, wherein the lid further comprises interconnections through the lid to interconnection contact pads on the silicon interconnect substrate.

25. A method for utilizing a semiconductor processing equipment comprising:

integrating electrical connectivity elements monolithically on a silicon backplane with the processing equipment, at least some of the connectivity elements to receive an integrated circuit (IC) chip, a technology to be used to manufacture the IC chip to produce a smaller minimum feature size than the technology of the processing equipment; and

integrating monolithically on the silicon backplane circuit with the processing equipment elements including micro electromechanical systems (MEMS) and passive components to interoperate with the IC chip to process a signal to be received by the resulting circuit.

26. A method according to claim 25, wherein integrating electrical connectivity elements on the silicon backplane includes integrating MEMS devices to bond a flip-chip mounted IC to the backplane.

27. A method according to claim 25, wherein integrating the electrical connectivity elements and the circuit elements comprises integrating the elements on the silicon backplane with processing equipment having lithographic technology to produce a 0.5 μ

m or larger feature size.

28. A method according to claim 25, wherein integrating the electrical connectivity elements and the circuit elements comprises integrating the elements to prepare the silicon backplane to produce a system on a chip integrated circuit.

29. An electronic system comprising:

a chip with an integrated circuit (IC) bonded to contact pads on a silicon interconnect backplane, the silicon backplane having integrated circuits including a micro electromechanical system (MEMS) device processed into the silicon backplane with the same processing used to create the contact pads, the processing different from a processing used to create the IC; and

a direct current power storage cell coupled with the chip to supply power to the chip.

30. A system according to claim 29, wherein the MEMS device further includes a microfluidic system.

31. A system according to claim 29, wherein the MEMS device further includes an actuation circuit device.

32. A system according to claim 29, wherein the circuit elements comprise sensor circuits.

33. A system according to claim 29, further comprising a cap processed onto the silicon backplane to hermetically isolate circuit elements on the silicon backplane.

34. A system according to claim 33, wherein the cap comprises a cap of silicon-based material.

35. A system according to claim 33, further comprising interconnections manufactured through the cap to provide electrical connectivity to contact pads on the silicon backplane.