Electronic circuit with embedded memory

• US 20050218521A1
• Filed: 03/29/2005
• Published: 10/06/2005
• Est. Priority Date: 06/21/2004
• Status: Active Grant

• Current Assignee: BeSang Inc.
• Original Assignee: Sang-Yun Lee
• Inventors: Lee, Sang-Yun
• Granted Patent: US 7,633,162 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/18 Peripheral circuit regions
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Circuitry includes first and second circuits spaced apart by an interconnect region. The interconnect region includes a first interconnect and the second circuit includes a stack of semiconductor layers. The first interconnect extends between the first and second circuits to provide communication therebetween. The second circuit operates as a memory circuit.

Claims

1. Circuitry comprising:

a first circuit;

an interconnect region;

a first interconnect included in the interconnect region; and

a second circuit spaced apart from the first circuit by the interconnect region, the second circuit including a stack of semiconductor layers; and

the first interconnect extending between the first and second circuits to provide communication therebetween.

2. The circuitry of claim 1 wherein the stack of semiconductor layers operates as a memory device.

3. The circuitry of claim 1 further including a third circuit positioned near the first circuit so that the second circuit is spaced apart from the first and third circuits by the interconnect region.

4. The circuitry of claim 3 further including a second interconnect extending through the interconnect region to provide communication between the first and third circuits.

5. The circuitry of claim 1 wherein the stack of semiconductor layers operates as a negative differential resistance static random access memory device.

6. The circuitry of claim 1 wherein at least a portion of the third circuit includes a crystalline semiconductor material region.

7. Circuitry comprising:

a substrate;

control circuitry carried by the substrate;

processor circuitry carried by the substrate and positioned near the control circuitry;

an interconnect region positioned on surfaces of the control and digital circuitry to provide communication therebetween; and

memory circuitry positioned on the interconnect region, the memory circuitry being formed from a stack of crystalline semiconductor materials, the interconnect region providing communication between the memory circuitry and the control circuitry.

8. The circuit of claim 7 wherein the memory circuitry includes a thyristor.

9. The circuit of claim 7 wherein the memory circuitry includes at least one negative differential resistance static random access memory device.

10. The circuitry of claim 7 wherein the memory circuitry includes reference, word, and bit lines which allow the control circuitry to communicate with the memory circuitry.

11. The circuitry of claim 10 wherein the memory circuitry includes at least one memory device which includes a stack of doped semiconductor layers, the stack of doped semiconductor layers extending between the reference and bit lines.

12. The circuitry of claim 7 wherein current flow through the stack of semiconductor layers is in a direction at a non-zero angle relative to the surface of the substrate.

13. The circuitry of claim 7, wherein current flow through the stack of semiconductor layers is in a direction substantially perpendicular to the surface of the substrate.

14. Circuitry comprising:

a substrate;

first and second processor circuits carried by the substrate;

a control circuit carried by the substrate and positioned near the first and second processor circuits;

an interconnect region carried by and extending from the substrate, the interconnect region allowing the first and second processor circuits to communicate with each other and the control circuit; and

a memory circuit positioned on the interconnect region, the memory circuit being electrically coupled to the control circuit through the interconnect region.

15. The circuit of claim 14 wherein the memory circuit is spaced apart from the control circuit and the first and second processor circuits by the interconnect region.

16. The circuit of claim 14 wherein the memory circuit is in communication with the first and second processor circuits through the control circuit.

17. The circuit of claim 14 wherein the control circuit communicates signals to and from the memory circuit and the first and second processor circuits.

18. The circuit of claim 14 wherein the control circuit is positioned between the first and second processor circuits.

19. The circuit of claim 14 wherein the control circuit extends around a portion of the outer periphery of the first and second processor circuits.

20. The circuitry of claim 14 wherein the memory circuit includes a memory device with a transistor.