Low moisture absorptive circuitized substrate with reduced thermal expansion, method of making same, electrical assembly utilizing same, and information handling system utilizing same

• US 20050218524A1
• Filed: 03/23/2005
• Published: 10/06/2005
• Est. Priority Date: 03/31/2004
• Status: Active Grant

• Current Assignee: TTM Technologies North America, LLC (TTM Technologies Incorporated)
• Original Assignee: Endicott Interconnect Technologies Incorporated
• Inventors: Memis, Irving, Papathomas, Kostas I., Japp, Robert M.
• Granted Patent: US 7,470,990 B2
• Time in Patent Office: Days
• US Class Current: 257/762
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/145 Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/3733 having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures H01L23/3732, H01L23/3737 take precedence
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/4922 having a heterogeneous or anisotropic structure
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0366 reinforced, e.g. by fibres, fabrics H05K1/036 takes precedence
• CPC Class Codes: H05K 1/0373 containing additives, e.g. fillers H05K1/036 takes precedence
• CPC Class Codes: H05K 2201/0209 Inorganic, non-metallic particles
• CPC Class Codes: H05K 2201/0278 Polymeric fibers
• CPC Class Codes: H05K 2201/068 wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: H05K 3/4626 characterised by the insulating layers or materials H05K3/4688 takes precedence
• CPC Class Codes: H05K 3/4652 Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence
• CPC Class Codes: H05K 3/4655 by using a laminate characterized by the insulating layer general-purpose insulating materials H05K1/03, H05K3/4673
• CPC Class Codes: H05K 3/4688 Composite multilayer circuits, i.e. comprising insulating layers having different properties having a special base or central core H05K3/4602

Abstract

A circuitized substrate including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, the second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof. The substrate further includes at least one electrically conductive layer as part thereof. An electrical assembly and a method of making the substrate are also provided, as is an information handling system (e.g., computer) incorporating the circuitized substrate of the invention as part thereof.

Claims

1. A circuitized substrate comprising:

a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, said second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof; and

at least one circuitized layer positioned on said composite layer.

2. The circuitized substrate of claim 1 wherein said low moisture absorptivity resin of said second dielectric sub-layer of said composite layer comprises a high Tg thermosetting polymer.

3. The circuitized substrate of claim 2 wherein said low moisture absorptivity resin of said second dielectric sub-layer of said composite layer has less than about 0.27% moisture absorption when immersed in water for a period of about 24 hours at a temperature of about 22°

C.

4. The circuitized substrate of claim 2 wherein said low moisture absorptivity resin of said second dielectric sub-layer of said composite layer comprises from about 10 to about 80 percent by weight of said second dielectric sub-layer.

5. The circuitized substrate of claim 1 wherein said first dielectric sub-layer of said composite layer further includes a low moisture absorptivity resin.

6. The circuitized substrate of claim 5 wherein said low moisture absorptivity resin of said first dielectric sub-layer of said composite layer comprises a high Tg thermosetting polymer.

7. The circuitized substrate of claim 1 wherein said first dielectric sub-layer of said composite layer has a coefficient of thermal expansion in the x and y direction less than about 15 ppm per °

C.

8. The circuitized substrate of claim 7 wherein said low moisture absorptivity resin of said first dielectric sub-layer of said dielectric composite layer has less than 0.27% moisture absorption when immersed in water for a period of about 24 hours at a temperature of about 22°

C.

9. The circuitized substrate of claim 7 wherein said low moisture absorptivity resin of said first dielectric sub-layer of said composite layer comprises from about 10 to about 80 percent by weight of said first dielectric sub-layer.

10. The circuitized substrate of claim 1 wherein said first and second dielectric sub-layers of said composite layer each include a plurality of thru-holes therein, the aspect ratio of the thickness of said circuitized substrate to the diameter of each of said thru-holes being within the range of from about 2:

1 to about 20;

1.

11. The circuitized substrate of claim 1 wherein said at least one circuitized layer is comprised of copper.

12. The circuitized substrate of claim 1 further including a second circuitized layer positioned on said composite layer on a side opposite said at least one circuitized layer.

13. The circuitized substrate of claim 12 further including second and third dielectric layers positioned on said at least one circuitized layer and said second circuitized layer, respectively, and third and fourth circuitized layers formed on said second and third dielectric layer, respectively.

14. The invention of claim 13 wherein said circuitized substrate comprises a chip carrier.

15. The circuitized substrate of claim 1 further including at least one one electrical component positioned on and electrically coupled to said circuitized substrate, said substrate and said component being an electrical assembly.

16. The circuitized substrate of claim 15 wherein said electrical component comprises a semiconductor chip.

17. The circuitized substrate of claim 15 wherein said electrical component comprises a chip carrier.

18. A method of making a circuitized substrate, said method comprising:

providing a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, said second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof, and

positioning at least one circuitized layer on said first dielectric sub-layer of said composite layer.

19. The method of claim 18 further including providing in said first and second dielectric sub-layers a plurality of thru-holes each having an aspect ratio of the thickness of said composite layer of said circuitized substrate to the diameter of said thru-hole within the range of from about 2:

1 to about 20;

1.

20. The method of claim 19 wherein said each of said plurality of thru-holes are provided within said first and second sub-layers using a laser.

21. The method of claim 18 further including positioning a second circuitized layer on said second dielectric sub-layer of said composite layer opposite said at least one circuitized layer.

22. The method of claim 21 further including providing second and third dielectric layers on said at least one circuitized layer and said second circuitized layer, respectively, and third and fourth circuitized layers formed on said second and third dielectric layer, respectively.

23. The method of claim 22 further including electrically coupling at least one electrical component to said at least one circuitized layer.

24. A multilayered circuitized structure comprising:

a first circuitized substrate portion including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, said second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on said composite layer, said first and second dielectric sub-layers including a first pattern of conductive thru-holes therein; and

second and third circuitized substrate portions positioned on opposite sides of said first circuitized substrate portion, each having a second pattern of interconnecting thru-holes therein, said first circuitized substrate portion providing electrical interconnection between said second and third circuitized substrate portions, including interconnecting selected ones of said thru-holes in said second circuitized substrate portion with corresponding thru-holes within said third circuitized substrate portion.

25. The invention of claim 24 wherein said multilayered circuitized structure comprises a printed circuit board.

26. The invention of claim 24 wherein said multilayered circuitized structure comprises a chip carrier.

27. The multilayered circuitized structure of claim 26 further including at least one semiconductor chip positioned on or within said chip carrier and forming part thereof.

28. An information handling system comprising:

a housing;

a circuitized substrate positioned substantially within said housing and including a composite layer including a first dielectric sub-layer including a plurality of fibers having a low coefficient of thermal expansion and a second dielectric sub-layer of a low moisture absorptivity resin, said second dielectric sub-layer not including continuous or semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on said composite layer; and

at least one electrical component positioned on and electrically coupled to said circuitized substrate.

29. The invention of claim 28 wherein said information handling system comprises a personal computer.

30. The invention of claim 28 wherein said information handling system comprises a mainframe computer.

31. The invention of claim 28 wherein said information handling system comprises a computer server.