Field programmable gate array logic cell and its derivatives
First Claim
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1. A logic cell, comprising:
- 3-input look-up tables, a plurality of cascading multiplexers at least one of which is a standard 2×
1 multiplexer, a plurality of switches, and a register, wherein the switches can provide feedback paths from the outputs to the inputs or by-pass paths from the inputs to the outputs.
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Abstract
The present invention relates to the general area of the Field Programmable Gate Arrays, and, in particular to the architecture and the structure of the building blocks of the Field Programmable Gate Arrays. The proposed logic cells offer, among other advantages, by-pass and feedback paths, fewer transistors, no need for dedicated carry logic or multiple registers, 3-input instead of 4-input look-up tables, easy implementation of up to 4-input logic functions, and multiplication.
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Citations
29 Claims
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1. A logic cell, comprising:
3-input look-up tables, a plurality of cascading multiplexers at least one of which is a standard 2×
1 multiplexer, a plurality of switches, and a register, wherein the switches can provide feedback paths from the outputs to the inputs or by-pass paths from the inputs to the outputs.- View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A field programmable gate array logic cell, comprising:
3-input look-up tables, multiplexers, switches, and flip-flops, wherein the switches may provide feedback paths from the outputs to the inputs or by-pass paths from the inputs to the outputs, and wherein at least one multiplexer is an ordinary multiplexer and the rest are hard-wired. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A field programmable gate array logic cell, comprising:
two 3-input look-up tables, one standard 2×
1 multiplexer, five hard-wired multiplexers, programmable transfer switches, a D flip-flop, wherein the switches may provide feedback paths from the outputs to the inputs or by-pass paths from the inputs to the outputs.- View Dependent Claims (16, 17, 18, 19)
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20. A field programmable gate array logic cell, comprising:
two 3-input look-up tables, one standard multiplexer, five hard-wired multiplexers, programmable transfer switches, a D flip-flop, and an AND gate, wherein the switches may provide feedback paths from the outputs to the inputs or by-pass paths from the inputs to the outputs. - View Dependent Claims (21, 22, 23)
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24. A logic cell, comprising:
look-up tables, cascading multiplexers, switches, a register, and an AND gate, wherein the switches may provide feedback paths from the outputs to the inputs or by-pass paths from the inputs to the outputs, and wherein at least one multiplexer is an ordinary multiplexer and the rest are hard-wired, and wherein the logic cell can be configured and partitioned to perform multiplication and logic functions of up to four inputs, and to operate as a 1-bit adder, an accumulator, an AOI/OAI, a 4-input look-up table, two 3-input look-up tables, two 2-input look-up tables, or one 2-input and one 3-input look-up table, where the look-up tables can separately operate in parallel and both the registered and the non-registered form of the logic cell outputs are available. - View Dependent Claims (25, 26, 27)
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28. A field programmable gate array logic cell means with 4 to 7 inputs and 2 outputs for performing, among other functions, logic functions of up to four inputs, and for operating as a 1-bit adder, an accumulator, an AOI/OAI, 2- or 3- or 4-input look-up tables, where the look-up tables can separately operate in parallel and in series and both the registered and the non-registered form of the logic cell outputs are available, and wherein the switches may provide feedback paths from the outputs to the inputs or by-pass paths from the inputs to the outputs, and at least one multiplexer is an ordinary multiplexer and the rest are hard-wired.
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29. A field programmable gate array logic cell means with 5 to 7 inputs and 2 outputs for performing, among other functions, logic functions of up to four inputs and multiplication, and for operating as a 1-bit adder, an accumulator, an AOI/OAI, 2- or 3- or 4-input look-up tables, where the look-up tables can separately operate in parallel and in series and both, the registered and the non-registered, forms of the logic cell outputs are available, and wherein the switches may provide feedback paths from the outputs to the inputs or by-pass paths from the inputs to the outputs, and at least one multiplexer is an ordinary multiplexer and the rest are hard-wired.
Specification