Multi-level voltage output control circuit and logic gate therefor

• US 20050218932A1
• Filed: 06/25/2004
• Published: 10/06/2005
• Est. Priority Date: 03/31/2004
• Status: Active Grant

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lim, Dae-Ho
• Granted Patent: US 7,068,075 B2
• Time in Patent Office: Days
• US Class Current: 326/81
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits

Abstract

A multi-level voltage output control circuit selectively outputs one of multi-level power voltages by driving gates of two MOS transistors, which act as switching devices for the multi-level power voltages, with two output signals, the two output signals having complementary phases to each other and generated from two logic gates receiving two input signals which have an identical timing and complementary phases to each other, wherein the two logic gates advance or slow down a rising timing and/or a falling timing of the two output signals by differently adjusting a size of PMOS transistors and that of NMOS transistors, which construct the logic gates, thereby excluding a case in which the two output signals are in a same logic state at the same time.

Claims

1. A multi-level voltage output control circuit for selectively outputting one of multi-level power voltages by driving gates of two PMOS transistors, which act as switching devices for the multi-level power voltages, with two output signals, wherein the two output signals have complementary phases to each other and generated from two NAND gates coupled with two input signals which have an identical timing and complementary phases to each other, which comprises:

the two NAND gates for advancing a rising timing and slowing down a falling timing of the two output signals, thereby excluding a case in which the two output signals are in a same logic state at the same time, by modulating sizes of PMOS transistors and NMOS transistors constructing the two NAND gates.

2. The multi-level voltage output control circuit as recited in claim 1, wherein at least one PMOS transistor included in the NAND gate has a threshold voltage V_T lowered by modulating a channel width W or a channel length L of the PMOS transistor.

3. The multi-level voltage output control circuit as recited in claim 2, wherein the channel width W of the PMOS transistor is widened to lower the threshold voltage V_T.

4. The multi-level voltage output control circuit as recited in claims 1, wherein at least one NOMS transistor included in the NAND gate has the threshold voltage V_T raised by adjusting a channel width W or a channel length L of the NMOS transistor.

5. The multi-level voltage output control circuit as recited in claims 2, wherein at least one NOMS transistor included in the NAND gate has the threshold voltage V_T raised by adjusting a channel width W or a channel length L of the NMOS transistor.

6. The multi-level voltage output control circuit as recited in claims 3, wherein at least one NOMS transistor included in the NAND gate has the threshold voltage V_T raised by adjusting a channel width W or a channel length L of the NMOS transistor.

7. The multi-level voltage output control circuit as recited in claim 4, wherein the channel length L of the NMOS transistor is lengthened to lower the threshold voltage V_T.

8. The multi-level voltage output control circuit as recited in claim 5, wherein the channel length L of the NMOS transistor is lengthened to lower the threshold voltage V_T.

9. The multi-level voltage output control circuit as recited in claim 6, wherein the channel length L of the NMOS transistor is lengthened to lower the threshold voltage V_T.

10. A multi-level voltage output control circuit for selectively outputting one of multi-level power voltages by driving gates of two NMOS transistors, which act as switching devices for the multi-level power voltages, with two output signals, wherein the two output signals have complementary phases to each other and generated from two NOR gates coupled with two input signals which have an identical timing and complementary phases to each other, which comprises:

the two NOR gates for slowing down a rising timing and advancing a falling timing of the two output signals, thereby excluding a case in which the two output signals are in a same logic state at the same time, by modulating sizes of PMOS transistors and NMOS transistors constructing the two NOR gates.

11. The multi-level voltage output control circuit as recited in claim 10, wherein at least one PMOS transistor included in the NOR gate has a threshold voltage V_T raised by modulating a channel width W or a channel length L of the PMOS transistor.

12. The multi-level voltage output control circuit as recited in claim 11, wherein the channel length L of the PMOS transistor is lengthened to raise the threshold voltage V_T.

13. The multi-level voltage output control circuit as recited in claim 10, wherein at least one NMOS transistor included in the NOR gate has the threshold voltage V_T lowered by adjusting a channel width W or a channel length L of the NMOS transistor.

14. The multi-level voltage output control circuit as recited in claim 11, wherein at least one NMOS transistor included in the NOR gate has the threshold voltage V_T lowered by adjusting a channel width W or a channel length L of the NMOS transistor.

15. The multi-level voltage output control circuit as recited in claim 12, wherein at least one NMOS transistor included in the NOR gate has the threshold voltage V_T lowered by adjusting a channel width W or a channel length L of the NMOS transistor.

16. The multi-level voltage output control circuit as recited in claim 13, wherein the channel width W of the NMOS transistor is widened to lower the threshold voltage V_T.

17. The multi-level voltage output control circuit as recited in claim 14, wherein the channel width W of the NMOS transistor is widened to lower the threshold voltage V_T.

18. The multi-level voltage output control circuit as recited in claim 15, wherein the channel width W of the NMOS transistor is widened to lower the threshold voltage V_T.

19. A NAND gate circuit for a multi-level voltage output control circuit including a first NAND gate receiving a first signal and a second NAND gate receiving a second signal which has an identical timing and a complementary phase to the first signal, thereby generating two output signals which have complementary phases to each other, wherein, for each of the first and the second NAND gate, at least one of PMOS transistors constituting the NAND gate has a channel width W relatively larger than its channel length L and NMOS transistors constructing the NAND gate have a channel length L relatively larger than their channel width W.

20. A NOR gate circuit for a multi-level voltage output control circuit including a first NOR gate receiving a first signal and a second NOR gate receiving a second signal which has an identical timing and a complementary phase to the first signal, thereby producing two output signals which have complementary phases to each other, wherein, for each of the first and the second NOR gate, PMOS transistors constituting the NOR gate have a channel width W relatively shorter than their channel length L and at least one of NMOS transistors constructing the NOR gate has a channel length L relatively shorter than its channel width W.