DELAY LINE SYNCHRONIZER APPARATUS AND METHOD

• US 20050218956A1
• Filed: 04/05/2004
• Published: 10/06/2005
• Est. Priority Date: 04/05/2004
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: LaBerge, Paul A.
• Granted Patent: US 6,980,042 B2
• Time in Patent Office: Days
• US Class Current: 327/291
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators

Abstract

A synchronizer system and method that can be used with a conventional adjustable delay circuit to preserve a pseudo-synchronous phase relationship between clock signals of different clock domains when the time delay of the adjustable delay circuit from which one of the clock signals is output is changed.

Claims

1. A method for generating a clock signal, comprising:

receiving a first clock signal;

generating a second clock signal based on the first clock signal, the second clock signal having a higher clock frequency than the first clock signal and further having a phase relationship with respect to the first clock signal related to a first time delay and relative to a rising or falling edge of the first clock signal;

adjusting the first time delay to which the phase relationship between the first and second clock signals is related to a second time delay;

monitoring the phase relationship between the first and second clock signals during adjustment of the first time delay to the second time delay; and

generating a third clock signal based on the first clock signal, the third clock signal having the clock frequency of the second clock signal and having a phase relationship with respect to the first clock signal related to the second time delay relative to the rising or falling edge to which the first time delay was relative.

2. The method of claim 1 wherein adjusting the first time delay to a second time delay comprises:

decoupling an input of a delay circuit from receiving an input clock signal;

providing control signals indicative of the second time delay to the delay circuit to change the first time delay to the second time delay; and

recoupling the input of the delay circuit to receive the input clock signal.

3. The method of claim 2 wherein adjusting the first time delay to a second time delay further comprises:

decoupling an output of the delay circuit from which the second clock signal is provided; and

recoupling the output of the delay circuit from which the third clock signal is provided following provision of the control signals indicative of the second time delay.

4. The method of claim 3 wherein decoupling the input of the delay circuit occurs before decoupling the output of the delay circuit.

5. The method of claim 3 wherein recoupling the output of the delay circuit occurs before recoupling the input of the delay circuit.

6. The method of claim 2 wherein monitoring the phase relationship between the first and second clock signals comprises:

in response to decoupling the input of the delay circuit, generating a synchronizing signal to monitor a clock transition of the first clock signal from which the last clock pulse of the second clock signal is based;

in response to recoupling the input of the delay circuit, ceasing generation of the synchronizing signal at a time relative to the clock transition monitored in response to decoupling to provide the third clock signal having a first clock pulse that maintains the phase relationship between the first and second clock signals.

7. The method of claim 1, further comprising generating a synchronized internal clock signal based on the first clock signal and wherein generating the second clock signal comprises delaying the synchronized internal clock signal by the first time delay.

8. A method of generating a clock signal based on a first clock signal, the method comprising:

generating an internal clock signal based on the first clock signal having a higher clock frequency than the first clock signal, the internal clock signal having an initial phase relationship relative to a clock edge of the first clock signal;

changing the initial phase relationship of the internal clock signal to the first clock signal to an adjusted phase relationship;

generating a phase synchronizer signal having a phase relationship relative to the first clock signal and a logic level to track the clock edge to which the initial phase relationship is relative; and

based on the phase synchronizer signal, generating the internal clock signal having the adjusted phase relationship and further having a first clock pulse relative to the same clock edge from which the initial phase relationship was relative.

9. The method of claim 8 wherein changing the initial phase relationship of the internal clock signal to the adjusted phase relationship comprises:

decoupling an input of a delay circuit having a first time delay from receiving an input clock signal generated based on the first clock signal;

providing control signals indicative of a second time delay to the delay circuit to change the first time delay to the second time delay; and

recoupling the input of the delay circuit to receive the input clock signal.

10. The method of claim 9 wherein changing the initial phase relationship of the internal clock signal to the adjusted phase relationship further comprises:

decoupling an output of the delay circuit from which the internal clock signal is provided; and

recoupling the output of the delay circuit from which the internal clock signal is provided following provision of the control signals indicative of the second time delay.

11. The method of claim 10 wherein decoupling the input of the delay circuit occurs before decoupling the output of the delay circuit.

12. The method of claim 10 wherein recoupling the output of the delay circuit occurs before recoupling the input of the delay circuit.

13. The method of claim 9 wherein monitoring the phase relationship between the first and second clock signals comprises:

in response to decoupling the input of the delay circuit, generating a synchronizing signal to monitor a clock transition of the first clock signal from which the last clock pulse of the second clock signal is based;

in response to recoupling the input of the delay circuit, ceasing generation of the synchronizing signal at a time relative to the clock transition monitored in response to decoupling to provide the third clock signal having a first clock pulse that maintains the phase relationship between the first and second clock signals.

14. The method of claim 8, further comprising generating a synchronized internal clock signal based on the first clock signal and wherein generating the internal clock signal comprises delaying the synchronized internal clock signal by a time delay.

15. A clock synchronizer circuit for coupling to a delay circuit, the delay circuit having an input and output and further having a control terminal to which control signals are applied to set a time delay of the delay circuit, the clock synchronizer circuit comprising:

a clock synchronizer input circuit having an input to which a clock synchronizer control signal is applied to initiate a clock synchronizer operation, a clock terminal to which a first clock signal is applied, and further having an output at which an initiate signal is provided in response to the first clock signal;

a first shift register having an input coupled to the output of the clock synchronizer input circuit, a clock terminal to which a second clock signal is applied, and further having an output providing an output signal in response to the second clock signal, the second clock signal having a higher clock frequency than the first clock signal;

a second shift register having an input coupled to the output of the first shift register, a clock terminal to which the second clock signal is applied, and further having an output providing an output signal in response to the second clock signal;

an input multiplexer control circuit having an input at which a trigger signal is provided, a clock terminal to which the second clock signal is applied, and further having an output at which an input multiplexer select signal is provided in response to the second clock signal, the input multiplexer select signal based on the trigger signal;

an input multiplexer having a first input to which the second clock signal is applied, a second input coupled to a reference voltage supply, an output terminal coupled to the input of the delay circuit, and further having a control terminal coupled to the output of the second multiplexer control circuit to couple the output terminal to the first or second inputs in response to the input multiplexer select signal; and

a clock phase tracking circuit having an input coupled to the output of the second shift register, a clock terminal to which the second clock signal is applied, and further having an output at which a trigger signal is provided, the clock phase tracking circuit operable to track a phase relationship of a last clock pulse of the internal clock signal relative to the first clock signal and, in response to the clock synchronizer control signal, further operable to output a trigger signal to cause the delay circuit to output a first clock pulse of the internal clock signal at a time relative to the first clock signal to maintain the tracked phase relationship.

16. The clock synchronizer circuit of claim 15 wherein the input multiplexer control circuit comprises a negative edge D flip-flop.

17. The clock synchronizer circuit of claim 15 wherein the clock synchronizer input circuit comprises a positive edge D flip-flop.

18. The clock synchronizer circuit of claim 15 wherein the clock phase tracking circuit comprises:

an AND logic gate having first and second inputs, and further having an output, the first input coupled to the output of the second shift register;

an OR logic gate having first and second inputs, and further having an output, the first input coupled to the output of the second shift register; and

a positive edge D flip-flop having an input coupled to the output of the AND logic gate, a true output coupled to the second input of the OR logic gate, and further having a not output coupled to the second input of the AND logic gate.

19. The clock synchronizer circuit of claim 15, further comprising:

a third shift register stage having an input coupled to the output of the second shift register, a clock terminal to which the second clock signal is applied, and further having an output providing an output signal in response to the second clock signal;

an output multiplexer control circuit having first and second input nodes coupled to the outputs of the first and second shift registers, respectively, and further having an output at which an output multiplexer select signal is provided based on the logic levels of the output signals of the first and second shift registers; and

an output multiplexer having a first input coupled to the output of the .delay circuit, a second output coupled to the reference voltage supply, an output terminal from which the internal clock signal is provided, and a control terminal coupled to the output of the first multiplexer control circuit to couple the output terminal to the first or second inputs in response to the output multiplexer select signal.

20. The clock synchronizer circuit of claim 19 wherein the output multiplexer control circuit comprises an AND logic gate.

21. The clock synchronizer of claim 15 wherein the first and second shift registers comprise a plurality of series coupled positive edge D flip-flops.

22. The clock synchronizer of claim 15 wherein the clock frequency of the second clock signal is a multiple of two of the clock frequency than the first clock signal.

23. The clock synchronizer of claim 15 wherein the clock frequency of the second clock signal is four times the clock frequency of the first clock signal.

24. A clock generator, comprising:

a delay circuit having input and output terminals, and further having a control terminal at which control signals are applied to set a time delay of the delay circuit; and

a synchronizer circuit having a synchronizer input circuit having an input to which a initiation signal is applied, a clock terminal to which a first clock signal is applied, and an output at which the initiation signal is coupled in response to the first clock signal;

a shift register having an input terminal coupled to the output of the synchronizer input circuit, an output terminal, and a clock terminal to which a second clock signal is applied, the shift register shifting a logic level applied to the input terminal to the output terminal in response to the second clock signal, the shift register further having an upstream tap and a downstream tap at which the logic level propagating through the shift register is coupled at first and second times, respectively;

an input multiplexer having a first input to which the second clock signal is applied, a second input coupled to a reference voltage supply, an output coupled to the input of the delay circuit, and further having a selection terminal, the input multiplexer selectively coupling the first or second input to the output according to an input multiplexer control signal; and

an input multiplexer control circuit having an input coupled to the downstream tap, a clock terminal to which the second clock signal is applied, and further having an output coupled to the selection terminal of the input multiplexer, in response to a first logic level coupled to the downstream tap, the input multiplexer control circuit operable to generate an input multiplexer control signal to couple the second input of the input multiplexer to its output and further operable to generate a phase synchronizer signal to track the phase relationship of the second clock signal relative to a rising or falling edge of the first clock signal, in response to a second logic level coupled to the downstream tap, the input multiplexer control circuit operable to generate an input multiplexer control signal based on the synchronizer signal to couple the first input of the input multiplexer to its output at a time to provide an output clock signal having a phase relationship relative to the rising or falling edge of the first clock signal tracked by the input multiplexer control circuit.

25. The clock generator of claim 24 wherein the synchronizer circuit further comprises:

an output multiplexer control circuit having a first input coupled to the upstream tap, a second input coupled to the output of the shift register, and further having an output at which an output multiplexer select signal is provided; and

an output multiplexer having a first input coupled to the output of the delay circuit, a second input coupled to the reference voltage supply, an output at which a internal clock signal is provided, and further having a selection terminal coupled to the output of the output multiplexer control circuit, the output multiplexer selectively coupling the first or second input to the output according to the output multiplexer select signal;

26. The clock generator of claim 25 wherein the output multiplexer control circuit comprises an AND logic gate.

27. The clock generator of claim 24 wherein the synchronizer input circuit of the synchronizer circuit comprises a positive edge D flip-flop.

28. The clock generator of claim 24 wherein the clock phase tracking circuit of the synchronizer circuit comprises:

an AND logic gate having first and second inputs, and further having an output, the first input coupled to the downstream tap of the shift register;

an OR logic gate having first and second inputs, and further having an output, the first input coupled to the downstream tap of the shift register;

a positive edge D flip-flop having an input coupled to the output of the AND logic gate, a true output coupled to the second input of the OR logic gate, and further having a not output coupled to the second input of the AND logic gate; and

a negative edge D flip-flop having an input coupled to the output of the OR logic gate and a true output at which the input multiplexer control signal is provided.

29. The clock generator of claim 24 wherein the shift register of the synchronizer circuit comprises a plurality of series coupled positive edge D flip-flops.

30. The clock generator of claim 24 wherein the clock frequency of the second clock signal is a multiple of two of the clock frequency than the first clock signal.

31. The clock generator of claim 24 wherein the clock frequency of the second clock signal is four times the clock frequency of the first clock signal.

32. A memory device, comprising:

an address bus;

a control bus;

a data bus;

an address decoder coupled to the address bus;

a read/write circuit coupled to the data bus;

a data driver circuit coupled to the data bus;

a control circuit coupled to the control bus;

a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; and

a clock generator coupled to the data driver to provide an internal clock signal, the clock generator comprising;

a delay circuit having input and output terminals, and further having a control terminal at which control signals are applied to set a time delay of the delay circuit; and

a synchronizer circuit having

a synchronizer input circuit having an input to which a initiation signal is applied, a clock terminal to which a first clock signal is applied, and an output at which the initiation signal is coupled in response to the first clock signal;

a shift register having an input terminal coupled to the output of the synchronizer input circuit, an output terminal, and a clock terminal to which a second clock signal is applied, the shift register shifting a logic level applied to the input terminal to the output terminal in response to the second clock signal, the shift register further having an upstream tap and a downstream tap at which the logic level propagating through the shift register is coupled at first and second times, respectively;

an input multiplexer having a first input to which the second clock signal is applied, a second input coupled to a reference voltage supply, an output coupled to the input of the delay circuit, and further having a selection terminal, the input multiplexer selectively coupling the first or second input to the output according to an input multiplexer control signal; and

an input multiplexer control circuit having an input coupled to the downstream tap, a clock terminal to which the second clock signal is applied, and further having an output coupled to the selection terminal of the input multiplexer, in response to a first logic level coupled to the downstream tap, the input multiplexer control circuit operable to generate an input multiplexer control signal to couple the second input of the input multiplexer to its output and further operable to generate a phase synchronizer signal to track the phase relationship of the second clock signal relative to a rising or falling edge of the first clock signal, in response to a second logic level coupled to the downstream tap, the input multiplexer control circuit operable to generate an input multiplexer control signal based on the synchronizer signal to couple the first input of the input multiplexer to its output at a time to provide an output clock signal having a phase relationship relative to the rising or falling edge of the first clock signal tracked by the input multiplexer control circuit.

33. The memory device of claim 32 wherein the synchronizer circuit further comprises:

an output multiplexer control circuit having a first input coupled to the upstream tap, a second input coupled to the output of the shift register, and further having an output at which an output multiplexer select signal is provided; and

an output multiplexer having a first input coupled to the output of the delay circuit, a second input coupled to the reference voltage supply, an output at which a internal clock signal is provided, and further having a selection terminal coupled to the output of the output multiplexer control circuit, the output multiplexer selectively coupling the first or second input to the output according to the output multiplexer select signal;

34. The memory device of claim 33 wherein the output multiplexer control circuit of the synchronizer circuit comprises an AND logic gate.

35. The memory device of claim 32 wherein the synchronizer input circuit of the synchronizer circuit comprises a positive edge D flip-flop.

36. The memory device of claim 32 wherein the clock phase tracking circuit of the synchronizer circuit comprises:

an AND logic gate having first and second inputs, and further having an output, the first input coupled to the downstream tap of the shift register;

an OR logic gate having first and second inputs, and further having an output, the first input coupled to the downstream tap of the shift register;

a positive edge D flip-flop having an input coupled to the output of the AND logic gate, a true output coupled to the second input of the OR logic gate, and further having a not output coupled to the second input of the AND logic gate; and

a negative edge D flip-flop having an input coupled to the output of the OR logic gate and a true output at which the input multiplexer control signal is provided.

37. The memory device of claim 32 wherein the shift register of the synchronizer circuit comprises a plurality of series coupled positive edge D flip-flops.

38. The memory device of claim 32 wherein the clock frequency of the second clock signal is a multiple of two of the clock frequency than the first clock signal.

39. The memory device of claim 32 wherein the clock frequency of the second clock signal is four times the clock frequency of the first clock signal.

40. A processor-based system, comprising:

a processor having a processor bus;

a system controller coupled to the processor bus, the system controller having a peripheral device port, the system controller further comprising a controller coupled to a system memory port;

at least one input device coupled to the peripheral device port of the system controller;

at least one output device coupled to the peripheral device port of the system controller;

at least one data storage device coupled to the peripheral device port of the system controller;

a memory bus coupled to the system controller for transmitting memory requests and responses thereon; and

a plurality of memory modules coupled to the memory bus, each of the modules having a plurality of memory devices and a memory hub coupled to the memory devices through a memory device bus to access the memory devices, the memory hub comprising;

a clock generator coupled to the data driver to provide an internal clock signal, the clock generator comprising;

a delay circuit having input and output terminals, and further having a control terminal at which control signals are applied to set a time delay of the delay circuit; and

a synchronizer circuit having

a synchronizer input circuit having an input to which a initiation signal is applied, a clock terminal to which a first clock signal is applied, and an output at which the initiation signal is coupled in response to the first clock signal;

a shift register having an input terminal coupled to the output of the synchronizer input circuit, an output terminal, and a clock terminal to which a second clock signal is applied, the shift register shifting a logic level applied to the input terminal to the output terminal in response to the second clock signal, the shift register further having an upstream tap and a downstream tap at which the logic level propagating through the shift register is coupled at first and second times, respectively;

an input multiplexer having a first input to which the second clock signal is applied, a second input coupled to a reference voltage supply, an output coupled to the input of the delay circuit, and further having a selection terminal, the input multiplexer selectively coupling the first or second input to the output according to an input multiplexer control signal; and

an input multiplexer control circuit having an input coupled to the downstream tap, a clock terminal to which the second clock signal is applied, and further having an output coupled to the selection terminal of the input multiplexer, in response to a first logic level coupled to the downstream tap, the input multiplexer control circuit operable to generate an input multiplexer control signal to couple the second input of the input multiplexer to its output and further operable to generate a phase synchronizer signal to track the phase relationship of the second clock signal relative to a rising or falling edge of the first clock signal, in response to a second logic level coupled to the downstream tap, the input multiplexer control circuit operable to generate an input multiplexer control signal based on the synchronizer signal to couple the first input of the input multiplexer to its output at a time to provide an output clock signal having a phase relationship relative to the rising or falling edge of the first clock signal tracked by the input multiplexer control circuit.

41. The processor-based system of claim 40 wherein the synchronizer circuit of the memory hub further comprises:

an output multiplexer control circuit having a first input coupled to the upstream tap, a second input coupled to the output of the shift register, and further having an output at which an output multiplexer select signal is provided; and

an output multiplexer having a first input coupled to the output of the delay circuit, a second input coupled to the reference voltage supply, an output at which a internal clock signal is provided, and further having a selection terminal coupled to the output of the output multiplexer control circuit, the output multiplexer selectively coupling the first or second input to the output according to the output multiplexer select signal;

42. The processor-based system of claim 41 wherein the output multiplexer control circuit of the synchronizer circuit comprises an AND logic gate.

43. The processor-based system of claim 40 wherein the synchronizer input circuit of the synchronizer circuit comprises a positive edge D flip-flop.

44. The processor-based system of claim 40 wherein the clock phase tracking circuit of the synchronizer circuit comprises:

an AND logic gate having first and second inputs, and further having an output, the first input coupled to the downstream tap of the shift register;

an OR logic gate having first and second inputs, and further having an output, the first input coupled to the downstream tap of the shift register;

a positive edge D flip-flop having an input coupled to the output of the AND logic gate, a true output coupled to the second input of the OR logic gate, and further having a not output coupled to the second input of the AND logic gate; and

a negative edge D flip-flop having an input coupled to the output of the OR logic gate and a true output at which the input multiplexer control signal is provided.

45. The processor-based system of claim 40 wherein the shift register of the synchronizer circuit comprises a plurality of series coupled positive edge D flip-flops.

46. The processor-based system of claim 40 wherein the clock frequency of the second clock signal is a multiple of two of the clock frequency than the first clock signal.

47. The processor-based system of claim 40 wherein the clock frequency of the second clock signal is four times the clock frequency of the first clock signal.

48. A memory hub, comprising:

a memory bus interface through which memory requests are received and memory responses are provided by the memory hub;

a local memory bus interface coupled to the memory bus interface through which memory device command, address and data signals are coupled, each signal having a timing relationship to at least one other signal;

a delay circuit coupled to the local memory bus interface to alter the timing relationship of at least one signal, the delay circuit having input and output terminals, and further having a control terminal at which control signals are applied to set a time delay of the delay circuit; and

a synchronizer circuit comprising;

a synchronizer input circuit having an input to which a initiation signal is applied, a clock terminal to which a first clock signal is applied, and an output at which the initiation signal is coupled in response to the first clock signal;

a shift register having an input terminal coupled to the output of the synchronizer input circuit, an output terminal, and a clock terminal to which a second clock signal is applied, the shift register shifting a logic level applied to the input terminal to the output terminal in response to the second clock signal, the shift register further having an upstream tap and a downstream tap at which the logic level propagating through the shift register is coupled at first and second times, respectively;

an input multiplexer having a first input to which the second clock signal is applied, a second input coupled to a reference voltage supply, an output coupled to the input of the delay circuit, and further having a selection terminal, the input multiplexer selectively coupling the first or second input to the output according to an input multiplexer control signal; and

an input multiplexer control circuit having an input coupled to the downstream tap, a clock terminal to which the second clock signal is applied, and further having an output coupled to the selection terminal of the input multiplexer, in response to a first logic level coupled to the downstream tap, the input multiplexer control circuit operable to generate an input multiplexer control signal to couple the second input of the input multiplexer to its output and further operable to generate a phase synchronizer signal to track the phase relationship of the second clock signal relative to a rising or falling edge of the first clock signal, in response to a second logic level coupled to the downstream tap, the input multiplexer control circuit operable to generate an input multiplexer control signal based on the synchronizer signal to couple the first input of the input multiplexer to its output at a time to provide an output clock signal having a phase relationship relative to the rising or falling edge of the first clock signal tracked by the input multiplexer control circuit.

49. The memory hub of claim 48 wherein the synchronizer circuit further comprises:

an output multiplexer control circuit having a first input coupled to the upstream tap, a second input coupled to the output of the shift register, and further having an output at which an output multiplexer select signal is provided; and

an output multiplexer having a first input coupled to the output of the delay circuit, a second input coupled to the reference voltage supply, an output at which a internal clock signal is provided, and further having a selection terminal coupled to the output of the output multiplexer control circuit, the output multiplexer selectively coupling the first or second input to the output according to the output multiplexer select signal;

50. The memory hub of claim 49 wherein the output multiplexer control circuit comprises an AND logic gate.

51. The memory hub of claim 48 wherein the synchronizer input circuit of the synchronizer circuit comprises a positive edge D flip-flop.

52. The memory hub of claim 48 wherein the clock phase tracking circuit of the synchronizer circuit comprises:

an AND logic gate having first and second inputs, and further having an output, the first input coupled to the downstream tap of the shift register;

an OR logic gate having first and second inputs, and further having an output, the first input coupled to the downstream tap of the shift register;

a positive edge D flip-flop having an input coupled to the output of the AND logic gate, a true output coupled to the second input of the OR logic gate, and further having a not output coupled to the second input of the AND logic gate; and

a negative edge D flip-flop having an input coupled to the output of the OR logic gate and a true output at which the input multiplexer control signal is provided.

53. The memory hub of claim 48 wherein the shift register of the synchronizer circuit comprises a plurality of series coupled positive edge D flip-flops.

54. The memory hub of claim 48 wherein the clock frequency of the second clock signal is a multiple of two of the clock frequency than the first clock signal.

55. The memory hub of claim 48 wherein the clock frequency of the second clock signal is four times the clock frequency of the first clock signal.