High precision analog to digital converter

• US 20050219105A1
• Filed: 05/31/2005
• Published: 10/06/2005
• Est. Priority Date: 05/10/2002
• Status: Active Grant

• Current Assignee: Guoxing Li, Liusheng Liu
• Original Assignee: Guoxing Li, Liusheng Liu
• Inventors: Li, Guoxing, Liu, Liusheng
• Granted Patent: US 7,196,652 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: H03M 3/34 by chopping
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/456 the modulator having a first order loop filter in the feedforward path

Abstract

An analog to digital converter may include an input switch array configured to alternately sample a first and a second input signal to a first and a second input capacitor during two different sample time intervals, an integrator having a first and second integration capacitor, and a cross switch array coupled to the input switch array and the integrator. The cross switch array may be configured to alternately transfer charges from the first and second input capacitors to the first and second integration capacitors during two different transfer time intervals. A system including an analog to digital converter consistent with an embodiment and an associated method of sampling and transferring charges in an analog to digital converter are also provided.

Claims

1. An analog to digital converter comprising:

an input switch array configured to alternately sample a first and a second input signal to a first and a second input capacitor during two different sample time intervals;

an integrator having a first and second integration capacitor; and

a cross switch array coupled to said input switch array and said integrator, said cross switch array configured to alternately transfer charges from said first and second input capacitors to said first and second integration capacitors during two different transfer time intervals.

2. The analog to digital converter of claim 1, wherein a first transfer time interval of said two different transfer time intervals occurs after a first sample time interval of said two different sample time intervals, and a second transfer time interval of said two different transfer time intervals occurs after a second sample time interval of said two different sample time intervals.

3. The analog to digital converter of claim 2, wherein said input switch array is configured to provide a first sample path to said first input capacitor from said first input signal and a second sample path to said second input capacitor from said second input signal during said first sample time interval.

4. The analog to digital converter of claim 3, wherein said input switch array is further configured to provide a third sample path to said second input capacitor from said first input signal and a fourth sample path to said first input capacitor from said second input signal during said second sample time interval.

5. The analog to digital converter of claim 2, wherein said cross switch array is configured to provide a first transfer path to said first integration capacitor from said first input capacitor and a second transfer path to said second integration capacitor from said second input capacitor during said first transfer time interval.

6. The analog to digital converter of claim 5, wherein said cross switch array is further configured to provide a third transfer path to said second integration capacitor from said first input capacitor and a fourth transfer path to said first integration capacitor from said second input capacitor during said second transfer time interval.

7. The analog to digital converter of claim 2, wherein said second transfer time interval is after said second sample time interval, and said second sample time interval is after said first transfer time interval, and said first transfer time interval is after said first sample time interval, and said first and second sample time intervals and said first and second transfer time interval are non-overlapping.

8. A system comprising:

a battery;

a sensor configured to sense a current to or from said battery and provide a first and second analog signal representative of said current;

an analog to digital converter configured to accept said first and second analog signals and provide a digital signal representative of a difference between said first and second analog signals, said analog to digital converter comprising;

an input switch array configured to alternately sample said first and second analog signals to a first and a second input capacitor during two different sample time intervals;

an integrator having a first and second integration capacitor; and

a cross switch array coupled to said input switch array and said integrator, said cross switch array configured to alternately transfer charges from said first and second input capacitors to said first and second integration capacitors during two different transfer time intervals.

9. The system of claim 8, wherein a first transfer time interval of said two different transfer time intervals occurs after a first sample time interval of said two different sample time intervals, and a second transfer time interval of said two different transfer time intervals occurs after a second sample time interval of said two different sample time intervals.

10. The system of claim 9, wherein said input switch array is configured to provide a first sample path to said first input capacitor from said first analog signal and a second sample path to said second input capacitor from said second analog signal during said first sample time interval.

11. The system of claim 10, wherein said input switch array is further configured to provide a third sample path to said second input capacitor from said first analog signal and a fourth sample path to said first input capacitor from said second analog signal during said second sample time interval.

12. The system of claim 9, wherein said cross switch array is configured to provide a first transfer path to said first integration capacitor from said first input capacitor and a second transfer path to said second integration capacitor from said second input capacitor during said first transfer time interval.

13. The system of claim 12, wherein said cross switch array is further configured to provide a third transfer path to said second integration capacitor from said first input capacitor and a fourth transfer path to said first integration capacitor from said second input capacitor during said second transfer time interval.

14. The system of claim 9, wherein said second transfer time interval is after said second sample time interval, and said second sample time interval is after said first transfer time interval, and said first transfer time interval is after said first sample time interval, and said first and second sample time intervals and said first and second transfer time interval are non-overlapping.

15. A method comprising:

alternately sampling a first and second input signal to a first and second input capacitor of an analog to digital converter during two different sampling time intervals; and

alternately transferring charges sampled during said two different sampling time intervals to a first and second integration capacitor of an integrator of said analog to digital converter during two different transfer time intervals.

16. The method of claim 15, wherein a first transfer time interval of said two different transfer time intervals occurs after a first sample time interval of said two different sample time-intervals, and a second transfer time interval of said two different transfer time intervals occurs after a second sample time interval of said two different sample time intervals.

17. The method of claim 16, further comprising:

providing a first sample path to said first input capacitor from said first input signal during said first sample time interval; and

providing a second sample path to said second input capacitor from said second input signal during said first sample time interval.

18. The method of claim 17, further comprising:

providing a third sample path to said second input capacitor from said first input signal during said second sample time interval; and

providing a fourth sample path to said first input capacitor from said second input signal during said second sample time interval.

19. The method of claim 16, further comprising:

providing a first transfer path to said first integration capacitor from said first input capacitor during said first transfer time interval; and

providing a second transfer path to said second integration capacitor from said second input capacitor during said first transfer time interval.

20. The method of claim 19, further comprising:

providing a third transfer path to said second integration capacitor from said first input capacitor during said second transfer time interval; and

providing a fourth transfer path to said first integration capacitor from said second input capacitor during said second transfer time interval, wherein said second transfer time interval occurs after said second sample time interval, and said second sample time interval occurs after said first transfer time interval, and said first transfer time interval occurs after said first sample time interval, and said first and second sample time intervals and said first and second transfer time interval are all non-overlapping.