Liquid crystal display device including driving circuit and method of fabricating the same

• US 20050219435A1
• Filed: 11/30/2004
• Published: 10/06/2005
• Est. Priority Date: 04/06/2004
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Hwang, Kwang-Sik, Oh, Kum-Mi
• Granted Patent: US 7,410,817 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS

Abstract

A method of fabricating an array substrate structure for a liquid crystal display device includes defining a display area and a non-display area on a substrate, the display area having a pixel TFT portion and a pixel electrode area, and the non-display area having an n-type driving TFT portion and a p-type driving TFT portion; forming a first gate electrode in the display area, a second and a third gate electrodes and a first capacitor electrode in the non-display area; an amorphous silicon layer on the substrate; crystallizing the amorphous silicon layer to a polycrystalline silicon layer and doping specific portions of the polycrystalline silicon layer with plurality of impurity concentrations; and forming a first semiconductor layer in the display area, a second and a third semiconductor layers and a second capacitor electrode in the non-display area.

Claims

1. A method of fabricating an array substrate structure for a liquid crystal display device, comprising:

sequentially disposing a transparent conductive material layer and a metallic material layer on a substrate defining a display area and a non-display area, the display area having a pixel TFT portion and a pixel electrode area, and the non-display area having an n-type driving TFT portion and a p-type driving TFT portion;

forming a first gate electrode in the pixel TFT portion, a second gate electrode in the n-type driving TFT portion, a third gate electrode in the p-type driving TFT portion, a gate line in the display area, a pixel electrode in the pixel electrode area, and a first capacitor electrode connected to the pixel electrode through a first mask process;

sequentially disposing a gate insulating layer and an amorphous silicon layer on the first gate electrode, the second gate electrode, the third gate electrode, the gate line, the pixel electrode and the first capacitor electrode;

doping the amorphous silicon layer in the p-type driving TFT portion with high concentration p-type impurities (p+) through a second mask process to define a first active region and a first ohmic contact region;

doping the amorphous silicon layer in the pixel TFT portion and the n-type driving TFT portion with high concentration n-type impurities (n+) and low concentration n-type impurities (n−

) through a third mask process to define second and third active regions, second and third ohmic contact regions, first and second lightly doped drain (LDD) regions and a storage capacitor area;

disposing a passivation layer on the amorphous silicon layer;

forming a first semiconductor layer in the pixel TFT portion, a second semiconductor layer in the n-type driving TFT portion, a third semiconductor layer in the p-type driving TFT portion, a second capacitor electrode in the storage capacitor area through a fourth mask process;

forming a passivation pattern on the first, second and third semiconductor layers and the second capacitor electrode through the fourth mask process, wherein side portions of each of the first, second and third semiconductor layers are exposed; and

forming first source and drain electrodes, second source and drain electrodes, third source and drain electrodes and a data line through a fifth mask process, portions of the first source and drain electrodes contacting the side portions of the first semiconductor layer, portions of the second source and drain electrodes contacting the side portions of the second semiconductor layer, portions of the third source and drain electrodes contacting the side portions of the third semiconductor layer, and the data line connected to the first source electrode.

2. The method according to claim 1, further comprising crystallizing the amorphous silicon layer to a polycrystalline silicon layer before doping with any impurities.

3. The method according to claim 1, wherein the gate insulating layer includes an inorganic insulating material.

4. The method according to claim 1, wherein the passivation layer includes an inorganic insulating material.

5. The method according to claim 1, wherein the first semiconductor layer includes the second active region, the second ohmic contact region and the first LDD region, the second semiconductor layer includes the third active region, the third ohmic contact region and the second LDD region, and the third semiconductor layer includes the first active region and the first ohmic contact region.

6. The method according to claim 5, wherein the first source and drain electrodes directly contact the second ohmic contact region, the second source and drain electrodes directly contact the third ohmic contact region, and the third source and drain electrodes contact the first ohmic contact region.

7. The method according to claim 1, wherein the first, second and third semiconductor layers and the passivation pattern disposed on the corresponding semiconductor layers form an island shape.

8. The method according to claim 1, wherein the first mask process includes:

forming a photoresist (PR) layer on the metallic material layer;

disposing a gate-pixel mask having a transmissive area, a blocking area and a half-transmissive area over the PR layer, a light transmittance of the half-transmissive is lower than that of the transmissive area and higher than that of the blocking area;

exposing the PR layer through the gate-pixel mask;

developing the PR layer to form a first gate-pixel PR pattern having a first thickness and a second gate-pixel PR pattern having a second thickness greater than the first thickness, the first gate-pixel PR pattern overlapping the first, second, and third gate electrodes, the pixel electrode, and the first capacitor electrode, and the second gate-pixel PR pattern overlapping the gate line;

sequentially etching the metallic material layer and the transparent conductive material layer using the first and second gate-pixel PR patterns as an etching mask;

removing the first gate-pixel PR pattern to expose the metallic material layer;

etching the metallic material layer to expose the transparent conductive material layer; and

removing the second gate-pixel PR pattern.

9. The method according to claim 8, wherein the PR layer has a positive type, the half-transmissive area corresponds to the first gate-pixel PR pattern and the blocking area corresponds to the second gate-pixel PR pattern.

10. The method according to claim 8, wherein removing the first gate-pixel PR pattern comprises removing a portion of the second gate-pixel PR pattern to reduce the second thickness.

11. The method according to claim 10, wherein removing the first gate-pixel PR pattern and partially removing the second gate-pixel PR pattern are performed anisotropically by at least one of ashing and stripping methods.

12. The method according to claim 1, wherein the gate line includes a double layer of the transparent conductive material layer and the metallic material layer.

13. The method according to claim 1, wherein the gate electrode includes a single layer of the transparent conductive material layer.

14. The method according to claim 1, further comprising disposing a buffer layer between the substrate and the transparent conductive material layer.

15. The method according to claim 14, wherein the buffer layer includes at least one of silicon nitride (SiNx) and silicon oxide (SiO₂).

16. The method according to claim 1, wherein the transparent conductive material layer includes at least one of indium-tin-oxide (ITO) and indium-zinc-oxide (IZO).

17. The method according to claim 1, wherein the transparent conductive material layer has a thickness within a range of about 500 Å

to about 1000 Å

.

18. The method according to claim 1, wherein the metallic material layer includes molybdenum (Mo).

19. The method according to claim 1, wherein the metallic material layer has a thickness less than about 3000 Å

.

20. The method according to claim 1, wherein the second mask process comprises:

forming a p+ PR pattern on the polycrystalline silicon layer, the p+ PR pattern exposing a portion of the polycrystalline silicon layer corresponding to the first ohmic contact region;

doping the exposed polycrystalline silicon layer with the high concentration p-type impurities using the p+ PR pattern as a doping mask; and

removing the p+ PR pattern.

21. The method according to claim 20, wherein the high concentration p-type impurities has a dose within a range of about 1×

10¹⁵ cm<sup>−

2</sup> to about 9×

10¹⁶ cm<sup>−

2</sup>.

22. The method according to claim 1, wherein the third mask process includes:

forming an n+ PR pattern on the polycrystalline silicon layer, the n+ PR pattern exposing first portions of the polycrystalline silicon layer corresponding to the second and third ohmic contact regions;

doping the exposed polycrystalline silicon layer with the high concentration n-type impurities using the n+ PR pattern as a doping mask;

removing portions of the n+ PR pattern to form an n−

PR pattern exposing a second portions of the polycrystalline silicon layer corresponding to the first and second LDD regions;

doping the polycrystalline silicon layer in the first and second LDD regions with the low concentration n-type impurities using the n−

PR pattern as a doping mask;

removing the n−

PR pattern.

23. The method according to claim 22, wherein the high concentration n-type impurities has a dose within a range of about 1×

10¹⁵ cm<sup>−

2</sup> to about 9×

10¹⁶ cm<sup>−

2</sup>, and the low concentration n-type impurities has a dose within a range of about 1×

10¹³ cm<sup>−

2</sup> to about 9×

10¹³ cm<sup>−

2</sup>.

24. The method according to claim 1, wherein the first drain electrode directly contacts the pixel electrode.

25. The method according to claim 1, wherein the fourth mask process includes:

disposing a PR layer on the passivation layer;

disposing a active-contact mask having a transmissive area, a blocking area and a half-transmissive area over the PR layer, and a light transmittance of the half-transmissive is lower than that of the transmissive area and higher than that of the blocking area;

exposing the PR layer using the active-contact mask;

developing the PR layer to form a first active-contact PR pattern having a first thickness and a second active-contact PR pattern having a second thickness smaller than the first thickness, the first active-contact PR pattern corresponding to the portions of the ohmic contact regions in each of the first, second and third semiconductor layers, the first active-contact PR pattern corresponding to other portions of each of the first, second and third semiconductor layers;

sequentially etching the passivation layer, the polycrystalline silicon layer and the gate insulating layer using the first and second active-contact PR patterns as an etching mask;

removing the second active-contact PR pattern to expose the passivation layer;

etching the passivation layer to expose the polycrystalline silicon layer corresponding to the portion of the ohmic regions in the first, second and third semiconductor regions; and

removing the first active-contact PR pattern.

26. The method according to claim 25, wherein the PR layer has a positive type photoresist, the half-transmissive area corresponds to the second active-contact PR pattern and the blocking area corresponds to the first active-contact PR pattern.

27. The method according to claim 25, wherein removing the second active-contact PR pattern includes partially removing the first active-contact PR pattern to reduce the second thickness.

28. The method according to claim 27, wherein removing the second active-contact PR pattern and partially removing the first active-contact PR pattern are performed anisotropically by at least one of ashing and stripping methods.

29. The method according to claim 25, wherein the second active-contact PR pattern further corresponds to the gate line, and wherein the first active-contact PR pattern further corresponds to the second capacitor electrode.

30. The method according to claim 29, further comprising removing the polycrystalline silicon layer using the passivation pattern formed underneath the first active-contact PR pattern as an etching mask.

31. A method of fabricating an array substrate structure for a liquid crystal display device, comprising:

sequentially disposing a transparent conductive material layer and a metallic material layer on a substrate defining a display area and a non-display area, the display area having a pixel TFT portion and a pixel electrode area, and the non-display area having a driving TFT portion;

forming a first gate electrode in the pixel TFT portion and a second gate electrode in the driving TFT portion, a gate line in the display area, a pixel electrode in the pixel electrode area through a first mask process, wherein a first capacitor electrode connects to the pixel electrode;

sequentially disposing a gate insulating layer and an amorphous silicon layer on the first, second gate electrodes, the gate line, the pixel electrode, and the first capacitor electrode;

doping the amorphous silicon layer with impurities through a second mask process to define a first active region, a first ohmic contact region, and storage capacitor area in the pixel TFT portion, and a second active region and a second ohmic contact region in the driving TFT portion;

disposing a passivation layer on the polycrystalline silicon layer;

forming a first semiconductor layer in the pixel TFT portion, a second semiconductor layer in the driving TFT portion, a second capacitor electrode in the storage capacitor area, and a passivation pattern on the first and second semiconductor layers and the second capacitor electrode through a third mask process, side portions of each of the first and second semiconductor layers are exposed using the passivation pattern; and

forming first source and drain electrodes, second source and drain electrodes, and a data line through a fourth mask process, the first source and drain electrodes contacting the side portions of the first semiconductor layer, the second source and drain electrodes contacting the side portions of the second semiconductor layer, and the data line connected to the first source electrode.

32. The method according to claim 31, wherein the impurities include at least one of n-type and p-type impurities.

33. The method according to claim 31, further comprising crystallizing the amorphous silicon layer to a polycrystalline silicon layer before doping with any impurities.

34. The method according to claim 31, wherein the first semiconductor layer includes the first active region and the first ohmic contact region, and the second semiconductor layer includes the second active region and the second ohmic contact region.

35. The method according to claim 34, wherein the first source and drain electrodes directly contact the first ohmic contact region, and the second source and drain electrodes directly contact the second ohmic contact region.

36. The method according to claim 31, wherein the first semiconductor layer, the second semiconductor layer and the passivation pattern formed on the corresponding semiconductor layer form an island shape.

37. The method according to claim 31, wherein the first mask process includes:

disposing a PR layer on the metallic material layer;

disposing a gate-pixel mask having a transmissive area, a blocking area and a half-transmissive area over the PR layer, a light transmittance of the half-transmissive area is lower than that of the transmissive area and higher than that of the blocking area;

exposing the PR layer using the gate-pixel mask;

developing the PR layer to form a first gate-pixel PR pattern having a first thickness and a second gate-pixel PR pattern having a second thickness greater than the first thickness, the first gate-pixel PR pattern overlapping the first and second gate electrodes, the pixel electrode, and the first capacitor electrode, the second gate-pixel PR pattern overlapping the gate line;

sequentially etching the metallic material layer and the transparent conductive material layer using the first and second gate-pixel PR patterns as an etching mask;

removing the first gate-pixel PR pattern to expose the metallic material layer;

etching the metallic material layer to expose the transparent conductive material layer; and

removing the second gate-pixel PR pattern.

38. The method according to claim 37, wherein the PR layer has a positive type photoresist, the half-transmissive area corresponds to the first gate-pixel PR pattern and the blocking area corresponds to the second gate-pixel PR pattern.

39. The method according to claim 37, wherein removing the first gate-pixel PR pattern includes removing a portion of the second gate-pixel PR pattern to reduce the second thickness.

40. The method according to claim 39, wherein removing the first gate-pixel PR pattern and removing the portion of the second gate-pixel PR pattern are performed anisotropically by at least one of ashing and stripping methods.

41. The method according to claim 31, further comprising disposing a buffer layer between the substrate and the transparent conductive material layer.

42. The method according to claim 31, wherein the second mask process comprises:

disposing a doping PR pattern on the polycrystalline silicon layer, the doping PR pattern exposing a portion of the polycrystalline silicon layer corresponding to the first and second ohmic contact regions;

doping the polycrystalline silicon layer with the impurities using the doping PR pattern as a doping mask; and

removing the doping pattern.

43. The method according to claim 31, wherein the fourth mask process includes:

forming a PR layer on the passivation layer;

disposing a active-contact mask having a transmissive area, a blocking area and a half-transmissive area over the PR layer, a light transmittance of the half-transmissive area is lower than that of the transmissive area and higher than that of the blocking area;

exposing the PR layer using the active-contact mask;

developing the PR layer to form a first active-contact PR pattern having a first thickness and a second active-contact PR pattern having a second thickness smaller than the first thickness, the second active-contact PR pattern corresponding to the portions of the ohmic contact regions in each of the first and second semiconductor layers, the first active-contact PR pattern corresponding to other portions of each of the first and second semiconductor layers;

sequentially etching the passivation layer, the polycrystalline silicon layer and the gate insulating layer using the first and second active-contact PR patterns as an etching mask;

removing the second active-contact PR pattern to expose the passivation layer;

etching the passivation layer to expose the polycrystalline silicon layer corresponding to the ohmic contact regions in the first and second semiconductor layers; and

removing the first active-contact PR pattern.

44. The method according to claim 43, wherein the PR layer has a positive type photoresist, wherein the half-transmissive area corresponds to the second active-contact PR pattern, and wherein the blocking area corresponds to the first active-contact PR pattern.

45. The method according to claim 43, wherein removing the second active-contact PR pattern includes partially removing the first active-contact PR pattern to reduce the first thickness.

46. The method according to claim 45, wherein removing the second active-contact PR pattern and partially removing the first active-contact PR pattern are performed anisotropically by at least one of ashing and stripping methods.

47. The method according to claim 43, wherein the second active-contact PR pattern further corresponds to the gate line, and wherein the first active-contact PR pattern further corresponds to the second capacitor electrode.

48. The method according to claim 47, further comprising removing the polycrystalline silicon layer using the passivation pattern formed underneath the first active-contact PR pattern as an etching mask.

49. An array substrate structure for a liquid crystal display device, comprising:

first, second and third gate electrodes on a substrate having a display area and a non-display area, the display area having a pixel TFT portion and a pixel electrode area, and the non-display area having an n-type driving TFT portion and a p-type driving TFT portion, the first gate electrode disposed in the pixel TFT portion, the second gate electrode disposed in the n-type driving TFT portion, the third gate electrode disposed in the p-type driving TFT portion;

a gate line in the display area on the substrate;

a pixel electrode in the pixel electrode area on the substrate;

a gate insulating layer on the first, second, and third gate electrodes, the gate line, and the pixel electrode;

first, second and third semiconductor layers of polycrystalline silicon on the gate insulating layer, the first semiconductor layer disposed in the pixel TFT portion, the second semiconductor layer disposed in the n-type driving TFT portion, and the third semiconductor layer disposed in the p-type driving TFT portion;

a passivation pattern on the first, second and third semiconductor layers, the passivation pattern exposing side portions of each of the first, second and third semiconductor layers;

first source and drain electrodes, second source and drain electrodes, and third source and drain electrodes on the substrate, the first source and drain electrodes contacting the side portions of the first semiconductor layer, the second source and drain electrodes contacting the side portions of the second semiconductor layer, the third source and drain electrodes contacting the side portions of the third semiconductor layer; and

a data line crossing the gate line and connected to the first source electrode.

50. The substrate structure according to claim 49, wherein the first, second and third gate electrodes and the pixel electrode include a single layer of a transparent conductive material.

51. The substrate structure according to claim 49, wherein the gate line includes a double layer of a transparent conductive material and a metallic material.

52. The substrate structure according to claim 49, further comprising a first capacitor electrode connected to the pixel electrode and a second capacitor electrode over the first capacitor electrode.

53. The substrate structure according to claim 52, wherein the first capacitor electrode includes a transparent conductive material, and wherein the second capacitor electrode includes the polycrystalline silicon material.

54. The substrate structure according to claim 49, wherein the first drain electrode directly contacts the pixel electrode.

55. The substrate structure according to claim 49, wherein the gate insulting layer and the passivation pattern have an island shape.