Radiation-hardened programmable device
First Claim
1. A method of converting a soft SRAM memory into a radiation hardened read-only memory, the method comprising:
- programming a data pattern into an SRAM memory;
irradiating the SRAM memory at a total dosage of between 300K and 1 Meg RAD in order to burn the data pattern into memory.
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Accused Products
Abstract
A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same manner as a reading and writing to a normal RAM memory, having the customer save the final debugged data pattern, delivering the data pattern to the factory, loading the customer-developed data pattern into memory, programming the customer-developed data pattern into a number of production circuits, irradiating the production circuits at a total dosage of between 300K and 1 Meg RAD to burn the data pattern into memory, and shipping the irradiated and programmed parts to the customer.
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Citations
22 Claims
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1. A method of converting a soft SRAM memory into a radiation hardened read-only memory, the method comprising:
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programming a data pattern into an SRAM memory;
irradiating the SRAM memory at a total dosage of between 300K and 1 Meg RAD in order to burn the data pattern into memory. - View Dependent Claims (2)
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3. A radiation-hardened SRAM memory cell comprising:
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complementary column select lines;
a row select line;
cross-coupled first and second P-channel transistors;
cross-coupled first and second N-channel transistors, the current paths of the first P-channel and first N-channel transistors being coupled together at a first node and the current paths of the second P-channel and second N-channel transistors being coupled together at a second node;
a pair of pass transistors for transferring a complementary data state from the first and second nodes to the complementary column select lines, wherein a gate of the first N-channel transistor is biased to ground and the gate of the second N-channel transistors is biased to VDD, the first and second N-channel transistors being irradiated to a sufficient dosage to establish a permanent data state in the memory cell. - View Dependent Claims (4, 5)
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6. A method of using a radiation-hardened integrated circuit comprising:
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receiving soft prototype memory devices;
developing a final, debugged, data pattern using the soft prototype memory devices;
shipping the final data pattern to the factory;
receiving irradiated pin-compatible production memory devices including a read-only version of the final data pattern from the factory. - View Dependent Claims (7, 8, 9)
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10. A radiation-hardened SRAM memory cell comprising:
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first and second nodes;
first and second transistors having current paths coupled at the first node, and gates coupled to the second node;
third and fourth transistors having current paths connected at the second node, and gates coupled to the first node, wherein the second and fourth transistors being irradiated with a sufficient dosage to induce a permanent complimentary data state at the first and second nodes. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A programmable key method comprising:
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providing a plurality of key circuits;
writing a data pattern into a plurality of key circuits; and
irradiating the key circuits at a total dosage of between 300K and 1 Meg RAD in order to burn the data pattern into memory. - View Dependent Claims (20, 21, 22)
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Specification