Radiation-hardened programmable device

• US 20050219891A1
• Filed: 05/19/2005
• Published: 10/06/2005
• Est. Priority Date: 10/23/2001
• Status: Active Grant

• Current Assignee: Aeroflex Colorado Springs Incorporated (Cobham PLC)
• Original Assignee: Aeroflex Colorado Springs Incorporated (Cobham PLC)
• Inventors: Gardner, Harry N., Kerwin, David
• Granted Patent: US 7,251,150 B2
• Time in Patent Office: Days
• US Class Current: 365/104
• CPC Class Codes: G11C 11/4125 Cells incorporating circuit means for protecting against loss of information
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A method of programming a radiation-hardened integrated circuit includes the steps of supplying a prototype device including an SRAM memory circuit or programmable key circuit to a customer, having the customer develop working data patterns in the field in the same manner as a reading and writing to a normal RAM memory, having the customer save the final debugged data pattern, delivering the data pattern to the factory, loading the customer-developed data pattern into memory, programming the customer-developed data pattern into a number of production circuits, irradiating the production circuits at a total dosage of between 300K and 1 Meg RAD to burn the data pattern into memory, and shipping the irradiated and programmed parts to the customer.

Claims

1. A method of converting a soft SRAM memory into a radiation hardened read-only memory, the method comprising:

programming a data pattern into an SRAM memory;

irradiating the SRAM memory at a total dosage of between 300K and 1 Meg RAD in order to burn the data pattern into memory.

2. The method of claim 1 further comprising shipping the irradiated and programmed parts to the customer.

3. A radiation-hardened SRAM memory cell comprising:

complementary column select lines;

a row select line;

cross-coupled first and second P-channel transistors;

cross-coupled first and second N-channel transistors, the current paths of the first P-channel and first N-channel transistors being coupled together at a first node and the current paths of the second P-channel and second N-channel transistors being coupled together at a second node;

a pair of pass transistors for transferring a complementary data state from the first and second nodes to the complementary column select lines,

wherein a gate of the first N-channel transistor is biased to ground and the gate of the second N-channel transistors is biased to VDD, the first and second N-channel transistors being irradiated to a sufficient dosage to establish a permanent data state in the memory cell.

4. A radiation-hardened memory cell as in claim 3 in which each of the pair of pass transistors comprise N-channel transistors.

5. A radiation-hardened memory cell as in claim 3 in which the first and second N-channel transistors have been exposed to a total dose or radiation between 300K and 1 MEG RADs.

6. A method of using a radiation-hardened integrated circuit comprising:

receiving soft prototype memory devices;

developing a final, debugged, data pattern using the soft prototype memory devices;

shipping the final data pattern to the factory;

receiving irradiated pin-compatible production memory devices including a read-only version of the final data pattern from the factory.

7. The method of claim 6 in which receiving soft prototype memory devices comprises receiving prototype memory devices including at least one SRAM memory cell.

8. The method of claim 6 in which receiving irradiated pin-compatible production memory devices comprises receiving production memory devices including at least one SRAM memory cell.

9. The method of claim 6 in which receiving irradiated pin-compatible production memory devices comprises receiving production memory devices that have been exposed to a total dose radiation of at least 300K Rads.

10. A radiation-hardened SRAM memory cell comprising:

first and second nodes;

first and second transistors having current paths coupled at the first node, and gates coupled to the second node;

third and fourth transistors having current paths connected at the second node, and gates coupled to the first node, wherein

the second and fourth transistors being irradiated with a sufficient dosage to induce a permanent complimentary data state at the first and second nodes.

11. The memory cell of claim 10 in which the second and fourth transistors each comprise N-channel transistors.

12. The memory cell of claim 10 in which the first and third transistors each comprise P-channel transistors.

13. The memory cell of claim 10 in which the gate of the second transistor is set to a logic one voltage and the gate of the fourth transistor is set to a logic zero voltage prior to irradiation.

14. The memory cell of claim 13 in which the logic one voltage is about 2.7 volts and the logic zero voltage is about zero volts.

15. The memory cell of claim 10 further comprising:

a pair of complementary column select lines;

means for coupling the complementary column select lines to the first and second nodes; and

a row select line coupled to the coupling means.

16. The memory cell of claim 15 in which the coupling means comprises first and second pass transistors.

17. The memory cell of claim 16 in which the first pass transistor comprises an N-channel transistor having a gate coupled to the row select line.

18. The memory cell of claim 16 in which the second pass transistor comprises an N-channel transistor having a gate coupled to the row select line.

19. A programmable key method comprising:

providing a plurality of key circuits;

writing a data pattern into a plurality of key circuits; and

irradiating the key circuits at a total dosage of between 300K and 1 Meg RAD in order to burn the data pattern into memory.

20. The method of claim 19 in which providing a plurality of key circuits comprises providing a plurality of circuits each including an N-channel transistor and a resistor coupled together in a source-follower amplifier configuration.

21. The method of claim 19 in which providing a plurality of key circuits comprises providing a plurality of circuits each including an N-channel transistor and a resistor coupled together in a common-source amplifier configuration.

22. The method of claim 19 in which providing a plurality of key circuits comprises providing a plurality of circuits each including an N-channel transistor and a P-channel transistor coupled together in a common-source amplifier configuration.