Non-volatile memory array

• US 20050219913A1
• Filed: 04/06/2004
• Published: 10/06/2005
• Est. Priority Date: 04/06/2004
• Status: Abandoned Application

• Current Assignee: O2ic, Inc.
• Original Assignee: O2ic, Inc.
• Inventors: Choi, Kyu Hyun, Li, Sheau-suey
• Application Number:
  US10/819,669
• Publication Number:
  US 20050219913A1
• Time in Patent Office: Days
• US Class Current: 365/185.290
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

Each non-volatile memory cell of an array of includes a guiding gate extending along a first portion of the cell'"'"'s channel and a control gate extending along a second portion of the cell'"'"'s channel. The first and second portions of the channel do not overlap. The guiding gate, which overlays the substrate above the channel, is insulated from the substrate via an oxide layer. The control gate, which also overlays the substrate above the channel region, is insulated from the substrate via an oxide-nitride-oxide layer. Each row of the array has a first terminal coupled to the guiding gates, and a second terminal coupled to the control gates of the cells disposed in that row. Each column of the array has a first terminal coupled to the drain regions, and a second terminal coupled to the source regions of the cells disposed in that column.

Claims

1. A non-volatile memory comprising:

N×

M non-volatile memory devices disposed in an array having N rows and M columns, each non-volatile memory device further comprising;

a substrate region;

a source region formed in the substrate region;

a drain region formed in the substrate region and separated from the source region by a channel region;

a first gate overlaying a first portion of the channel and separated therefrom via a first insulating layer; and

a second gate overlaying a second portion of the channel and separated therefrom via a second insulating layer;

wherein said first portion of the channel and said second portion of the channel do not overlap,

wherein each row of the array has a first associated terminal coupled to the first gates of the non-volatile devices disposed in that row, and a second associated terminal coupled to the second gates of the non-volatile devices disposed in that row, wherein each column of the array has a first associated terminal coupled to the drain regions of the non-volatile devices disposed in that column, and a second associated terminal coupled to the source regions of the non-volatile devices disposed in that column.

2. The non-volatile memory of claim 1 wherein to erase the non-volatile device disposed in row R, and column C of the M×

N array, a relatively high first negative voltage is applied to the first terminal associated with row R, a second negative voltage greater than the first negative voltage is applied to the second terminal associated with row R, and a third voltage is applied to the first terminal associated with column C.

3. The non-volatile memory of claim 2 wherein the second terminal associated with column C is supplied with the third voltage.

4. The non-volatile memory of claim 2 wherein the second terminal associated with column C is caused to float.

5. The non-volatile memory of claim 1 wherein to erase the non-volatile device disposed in row R, and column C of the M×

N array, a first negative voltage is applied to the first terminal associated with row R, a second voltage greater than the first negative voltage is applied to the second terminal associated with row R, a relatively high third positive voltage is applied to the first terminal associated with column C, and a fourth voltage less than the third positive voltage is applied to the second terminal associated with column C.

6. The non-volatile memory of claim 1 wherein to program the non-volatile device disposed in row R, and column C of the M×

N array, a first relatively high positive voltage is applied to the second terminal associated with row R, a second voltage less than the first voltage is applied to the first terminal associated with row R and to the second terminal associated with column C, and a third voltage greater than or equal to the second voltage is applied to the first terminal associated with column C.

7. The non-volatile memory of claim 1 wherein to program the non-volatile device disposed in row R, and column C of the M×

N array, a first relatively high positive voltage is applied to the first terminal associated with row R, a second positive voltage greater than the first voltage is applied to the second terminal associated with row R, a third voltage less than the second voltage is applied to the first terminal associated with column C, and a fourth voltage less than the third voltage and smaller than the first voltage is applied to the second terminal associated with column C.

8. The non-volatile memory of claim 1 wherein to read the non-volatile device disposed in row R, and column C of the M×

N array, a first positive supply voltage is applied to the first terminal associated with row R, a second voltage in the range of one-half to the positive supply voltage is applied to the second terminal associated with row R, and a third voltage in the range of one-third of the supply voltage to two-third of the supply voltage is applied first terminal associated with column C.

9. The non-volatile memory of claim 1 wherein in each non-volatile memory device, said first insulating layer is an oxide layer.

10. The non-volatile memory of claim 9 wherein for each non-volatile memory device, said second insulating layer further comprises a first oxide layer formed over said channel region, a first nitride layer formed over said first oxide layer of the second insulating region, and a second oxide layer formed over said first nitride layer.

11. The non-volatile memory of claim 10 wherein for each non-volatile memory device, said first oxide layer of the first insulating layer is thinner than the first oxide layer of the second insulating layer.

12. The non-volatile memory of claim 10 wherein for each non-volatile memory device, said first oxide layer of the first insulating layer is thicker than the first oxide layer of the second insulating layer.

13. The non-volatile memory of claim 11 wherein for each non-volatile memory device, said first gate extends partially over the second gate.

14. The non-volatile memory of claim 12 wherein for each non-volatile memory device, said second gate extends partially over the first gate.

16. The non-volatile memory of claim 1 wherein said substrate region is a p-type region formed in a n-well region.

15. The non-volatile memory of 6 wherein a channel connecting the source region to the drain region is formed in the substrate region of the non-volatile memory device being programmed.