Constellation mapping apparatus and method

• US 20050220205A1
• Filed: 05/20/2005
• Published: 10/06/2005
• Est. Priority Date: 10/10/2002
• Status: Active Grant

• Current Assignee: Hun-Sik Kang, Jong Won Kim
• Original Assignee: Hun-Sik Kang, Jong Won Kim
• Inventors: Kim, Jong-won, Kang, Hun-sik
• Granted Patent: US 7,480,338 B2
• Time in Patent Office: Days
• US Class Current: 375/265
• CPC Class Codes: H04L 27/36 Modulator circuits; Transmitter circuits

Abstract

A constellation mapping apparatus, which can reduce the storage capacity of a memory to one fourth by only storing constellation points in one quadrant of each constellation map rather than storing all the constellation points in each of the constellation maps, is provided. The constellation mapping apparatus includes a memory, an address generation block, a complementation logic block, and a scaling block. In the memory, constellation values in one of four quadrants of each constellation. The address generation block receives constellation point data, bits-per-symbol information, and valid symbol information indicating whether or not the bits-per-symbol information is valid, and generates address information of the memory where the constellation values corresponding to the constellation point data are stored and quadrant information indicating a quadrant where the constellation point data are placed. Based on the quadrant information for the constellation point data, the complementation logic block complements or does not complement the constellation values read from the memory following the address information. The scaling block outputs an output of the complementation logic block or a value obtained by multiplying the output of the complementation logic block by a predetermined gain obtained based on a baud rate, which indicates a speed of transmitting the bits-per-symbol information.

Claims

1. A constellation mapping method comprising:

receiving constellation point data, bits-per-symbol information, and valid symbol information indicating whether or not the bits-per-symbol information is valid;

generating address information of a memory, in which constellation values corresponding to the constellation point data are stored;

outputting an output of the memory or a result of complementing the output of the memory by generating real numbers and imaginary numbers in one of four quadrants of a constellation based on the address information of the memory; and

selectively outputting the value output in the previous step or a value obtained by multiplying the output value by a predetermined gain.

2. The constellation mapping method of claim 1 further comprising storing the selectively output value or performing retiming on the selectively output value for a following block.

3. The constellation mapping method of claim 1, wherein generating the address information of the memory, comprises;

generating a base address;

generating an index address; and

adding the base address and the index address.

4. The constellation mapping method of claim 3, wherein generating the base address, comprises:

receiving bits-per-symbol information and valid symbol information and selectively outputting a value of the bits-per-symbol information or 0 depending on a value of the valid symbol information; and

shifting a binary number ‘

00000001’

by as much as the selectively output value.

5. The constellation mapping method of claim 3, wherein generating the index address, comprises;

subtracting a predetermined value from the value generated in generating the base address;

shifting the input data by as much as the result of the subtraction; and

receiving data obtained by selecting lower six bits of the result of the shifting and coupling a most significant bit among the selected lower six bits with a binary number ‘

00000’

, data obtained by coupling fifth and fourth bits among the selected lower six bits with a binary number ‘

0000’

, data obtained by coupling the fifth bit through a third bit among the selected lower six bits with a binary number ‘

000’

, data obtained by coupling the fifth bit through a second bit among the selected lower six bits with a binary number ‘

00’

, data obtained by coupling the fifth bit through a firth bit among the selected lower six bits with a binary number ‘

0’

, a binary number ‘

000000’

, and receiving the value output in generating the base address via a selection port.

6. A computer-readable recording medium, on which the method of claim 1 is written in computer-readable program codes which can be processed in a computer.