Method for making self-coplanarity bumping shape for flip chip

• US 20050221535A1
• Filed: 06/03/2005
• Published: 10/06/2005
• Est. Priority Date: 02/27/2001
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Chippac Company Limited
• Inventors: Kweon, Young-Do, Pendse, Rajendra D., Kim, Kyung-Moon, Ahmad, Nazir
• Granted Patent: US 7,407,877 B2
• Time in Patent Office: Days
• US Class Current: 438/118
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/1184 involving a mechanical process, e.g. planarising the bump connector
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool. Also, a method for forming an interconnect between a first member and a second member of an electronic package includes providing one of the members with the stud bumps of the invention and then bringing the corresponding bumps and pads together in a bonding process, the compliance of the stems portions of the bumps accommodating the variance from coplanarity of the pad surfaces.

Claims

1. A method for forming a stud bump on a contact surface, comprising forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface.

2. The method of claim 2 wherein the tail portion, at least, is formed using a wire bonding tool, and the conical tail is dimensioned so that after truncating, the resulting top surface of the stem portion has a diameter at least about the same as a specified wire diameter and no greater than the diameter of the base.

4. The method of claim 2 wherein the truncating includes chemical mechanical polishing.

3. The method of claim 3 wherein the conical tail is dimensioned so that after truncating, the resulting top surface of the stem portion has a diameter at least about twice a specified wire diameter.

5. A method for forming an interconnect between a first member and a second member of an electronic package, comprising

providing a plurality of stud bumps on contact sites at specified locations on the first member, the stud bumps each having a base portion and having a stem portion that is more compliant than the base portion, the stem portion having a transverse planar top surface;

providing a second member having a plurality of bonding pads at specified locations on a surface of the second member, the respective specified locations on the first and second members corresponding;

apposing the first and second members such that the corresponding bumps and pads are aligned; and

bringing the first and second members together under conditions that promote bonding of the pumps onto the respective metal pads.

6. The method of claim 5 wherein one of the first and the second members comprises an integrated circuit chip.

7. The method of claim 5 wherein one of the first and the second members comprises a printed circuit substrate.

8. A method for making a flip chip semiconductor device package, comprising

providing a plurality of stud bumps on contact sites at specified locations on an integrated circuit chip, the stud bumps each having a base portion and having a stem portion that is more compliant than the base portion, the stem portion having a transverse planar top surface;

providing a substrate having a plurality of bonding pads at specified locations on a surface of the substrate, the respective specified locations on the integrated circuit chip and the substrate corresponding;

apposing the integrated circuit chip and the substrate such that the corresponding bumps and pads are aligned; and

bringing the integrated circuit chip and the substrate together under conditions that promote bonding of the pumps onto the respective metal pads.