Ultra thin back-illuminated photodiode array fabrication methods

• US 20050221541A1
• Filed: 05/24/2005
• Published: 10/06/2005
• Est. Priority Date: 06/25/2003
• Status: Active Grant

• Current Assignee: Array Optronix, Inc.
• Original Assignee: Array Optronix, Inc.
• Inventors: Goushcha, Alexander O., Metzler, Richard A.
• Granted Patent: US 7,462,553 B2
• Time in Patent Office: Days
• US Class Current: 438/142
• CPC Class Codes: H01L 27/1446 in a repetitive configuration
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y10S 438/963 Removing process residues from vertical substrate surfaces

Abstract

Ultra thin back-illuminated photodiode array fabrication methods providing backside contact by diffused regions extending through the array substrate. In accordance with the methods, a matrix is diffused into one surface of a substrate, and at a later stage of the substrate processing, the substrate is reduced in thickness and a similar matrix is diffused into the substrate from the other side, this second diffusion being aligned with the first and contacting the first within the substrate. These two contacting matrices provide good electrical contact to a conductive diffusion on the backside for a low resistance contact to the backside. Various embodiments are disclosed.

Claims

1. A method of fabricating a photodiode array comprising:

providing a semiconductor substrate having first and second surfaces;

providing a first matrix of regions of a first conductivity type of a higher conductivity than the substrate, including a high temperature diffusion, the first matrix of regions extending into the substrate from the first surface;

providing a plurality of regions of the second conductivity type interspersed within the first matrix of regions of the first conductivity type, including an additional high temperature diffusion, the second region extending into the substrate from the first surface a shorter distance than the first region;

grinding the substrate from the second surface to reduce the thickness of the substrate and to not expose the matrix of regions of a first conductivity type or the plurality of regions of the second conductivity type at the second surface of the substrate;

providing a second matrix of regions of a first conductivity type of a higher conductivity than the substrate extending into the substrate from the second surface, including a high temperature diffusion, the second matrix being aligned with the first matrix;

providing a layer of the first conductivity type having a conductivity greater than the substrate on the second surface of the substrate;

the first matrix of regions of a first conductivity type and the second matrix of regions of a first conductivity type contacting each other within the substrate; and

,

providing a plurality of electrical contacts at the first surface for the first region in the form of a matrix of regions of a first conductivity type and the plurality of regions of the second conductivity type.

2. The method of claim 1 wherein providing a semiconductor substrate comprises providing a semiconductor substrate of a first conductivity type.

3. The method of claim 1 wherein providing a semiconductor substrate comprises providing a semiconductor substrate of a second conductivity type.

4. The method of claim 1 wherein the layer of the first conductivity type having a conductivity greater than the substrate on the second surface of the substrate is provided by implantation.

5. The method of claim 1 wherein the substrate is ground to a thickness that separates the plurality of regions of the second conductivity type from the second surface of the substrate by an amount that approximately equals the depletion depth for the substrate at zero bias.

6. The method of claim 5 wherein the substrate provided is an n-type silicon substrate having a resistivity of approximately 400 ohm-cm.

7. The method of claim 5 wherein the substrate provided is a p-type silicon substrate.

8. The method of claim 1 wherein the plurality of regions of the second conductivity type are separated from the second surface of the substrate by approximately 9 μ

m.

9. The method of claim 1 wherein the plurality of contacts are a plurality of ball grid contacts.

10. The method of claim 9 wherein the plurality of contacts are of substantially equal size evenly distributed across the photodiode array.

11. The method of claim 1 wherein the substrate is ground to a thickness of less than approximately 50 μ

m.

12. The method of claim 1 wherein the substrate is ground to a thickness of approximately 30 μ

m.

13. A method of fabricating a photodiode array comprising:

providing a silicon substrate of a first conductivity type having first and second surfaces;

providing a matrix of regions of a first conductivity type of a higher conductivity than the substrate, including a high temperature diffusion, the first region extending into the substrate from the first surface;

providing a plurality of regions of the second conductivity type interspersed within the matrix of regions of the first conductivity type, including an additional high temperature diffusion, the second region extending into the substrate from the first surface a shorter distance than the first region;

providing additional doping of the first region, including a further high temperature diffusion;

grinding the substrate from the second surface to reduce the thickness of the substrate to less than approximately 50 μ

m and to not expose the matrix of regions of a first conductivity type and the plurality of regions of the second conductivity type at the second surface of the substrate;

providing a second matrix of regions of a first conductivity type of a higher conductivity than the substrate extending into the substrate from the second surface, including a high temperature diffusion, the second matrix being aligned with the first matrix;

providing a layer of the first conductivity type having a conductivity greater than the substrate on the second surface of the substrate;

the first matrix of regions of a first conductivity type and the second matrix of regions of a first conductivity type contacting each other within the substrate; and

,

providing a plurality of electrical contacts at the first surface for the first region in the form of a matrix of regions of a first conductivity type and the plurality of regions of the second conductivity type.

14. The method of claim 13 wherein providing a silicon substrate comprises providing a silicon substrate of a first conductivity type.

15. The method of claim 13 wherein providing a silicon substrate comprises providing a silicon substrate of a second conductivity type.

16. The method of claim 13 wherein the layer of the first conductivity type having a conductivity greater than the substrate on the second surface of the substrate is provided by implantation.

17. The method of claim 13 wherein the substrate is ground to a thickness that separates the plurality of regions of the second conductivity type from the second surface of the substrate by an amount that approximately equals the depletion depth for the substrate at zero bias.

18. The method of claim 17 wherein the substrate provided is an n-type silicon substrate having a resistivity of approximately 400 ohm-cm.

19. The method of claim 17 wherein the substrate provided is an p-type silicon substrate.

20. The photodiode array of claim 13 wherein the plurality of regions of the second conductivity type are separated from the second surface of the substrate by approximately 9 μ

m.

21. The method of claim 13 wherein the plurality of contacts are a plurality of ball grid contacts.

22. The method of claim 21 wherein the plurality of contacts are of substantially equal size evenly distributed across the photodiode array.

23. The method of claim 13 wherein the substrate is ground to a thickness of approximately 30 μ

m.

24. A method of fabricating a semiconductor device comprising:

providing a semiconductor substrate of a first conductivity type having first and second surfaces;

forming the semiconductor device on a first surface of the semiconductor substrate, including forming first deep diffusions extending into the substrate from the first surface;

forming second deep diffusions extending into the substrate from the second surface, the second deep diffusions being in the same pattern as the first deep diffusions;

forming a blanket region of the same conductivity type as the deep diffusions on the second surface of the substrate;

the second deep diffusions contacting the first deep diffusions within the substrate.

25. The method of claim 24 wherein the substrate, the first and second deep diffusions and the blanket region are of a first conductivity type.

26. The method of claim 24 wherein the first deep diffusions are deeper than diffusions of the semiconductor device.

27. A method of fabricating a semiconductor device comprising:

providing a semiconductor substrate of a first conductivity type; and

,

forming the semiconductor device on a first surface of the semiconductor substrate, including forming first deep diffusions;

forming second deep diffusions on a second surface of the substrate in the same pattern and of the same conductivity type as the first deep diffusions, the first and second deep diffusions being in contact within the substrate.

28. The method of claim 27 wherein the first deep diffusions are deeper than diffusions of the semiconductor device.