Semiconductor integrated circuit device and method for manufacturing the same
First Claim
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1. A semiconductor integrated circuit device comprising:
- a semiconductor substrate including an SRAM region and a ROM region;
a plurality of SRAM memory cells, each of which is formed in the SRAM region and includes a flip-flop, a pair of first conductivity type access transistors connected to the flip-flop and a pair of SRAM bit lines connected to the paired access transistors, respectively; and
a plurality of ROM memory cells, each of which is formed in the ROM region and includes a first conductivity type ROM transistor and a ROM bit line connected to the ROM transistor, wherein the SRAM memory cells connected to each pair of SRAM bit lines are smaller in number than the ROM memory cells connected to the ROM bit line and the ROM transistor has a larger channel width than the access transistors.
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Abstract
A semiconductor integrated circuit device includes a semiconductor substrate and a ROM region, an SRAM region and a peripheral circuit region which are formed on the semiconductor substrate. Further, a column switch region is provided adjacent to the ROM region. MOS transistors in the ROM region and channel regions of access transistors in the SRAM region have substantially the same p-type impurity concentration. Accordingly, the threshold voltages of the transistors are adjusted by making use of the great dependence of the threshold voltage of the transistor on the channel width.
9 Citations
9 Claims
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1. A semiconductor integrated circuit device comprising:
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a semiconductor substrate including an SRAM region and a ROM region;
a plurality of SRAM memory cells, each of which is formed in the SRAM region and includes a flip-flop, a pair of first conductivity type access transistors connected to the flip-flop and a pair of SRAM bit lines connected to the paired access transistors, respectively; and
a plurality of ROM memory cells, each of which is formed in the ROM region and includes a first conductivity type ROM transistor and a ROM bit line connected to the ROM transistor, wherein the SRAM memory cells connected to each pair of SRAM bit lines are smaller in number than the ROM memory cells connected to the ROM bit line and the ROM transistor has a larger channel width than the access transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 9)
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8. A method for manufacturing a semiconductor integrated circuit, device comprising the steps of:
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(a) preparing a semiconductor substrate including a ROM region, a ROM column switch region, an SRAM region and a peripheral circuit region, forming a first resist on the ROM column switch region and implanting first conductivity type impurities using the first resist as a mask to form an impurity region at the top of the ROM region, SRAM region and peripheral circuit region;
(b) forming a second resist on the ROM column switch region and the peripheral circuit region and implanting first conductivity type impurities using the second resist as a mask to form a high concentration impurity region at the top of the ROM region and the SRAM region; and
(c) forming second conductivity type transistors in the ROM region, ROM column switch region, SRAM region and peripheral circuit region, respectively, wherein in the step (c), the channel widths of the transistors are adjusted to determine the threshold voltages of the transistors, respectively.
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Specification