Interconnect structure for an integrated circuit and method of fabrication

• US 20050221604A1
• Filed: 05/31/2005
• Published: 10/06/2005
• Est. Priority Date: 09/30/2002
• Status: Active Grant

• Current Assignee: Hyun-Mog Park, Jose Maiz, Jun He
• Original Assignee: Hyun-Mog Park, Jose Maiz, Jun He
• Inventors: Maiz, Jose, He, Jun, Park, Hyun-Mog
• Granted Patent: US 7,151,051 B2
• Time in Patent Office: Days
• US Class Current: 438/622
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.

Claims

1-10. -10. (canceled)

11. A method for providing an interconnect structure for an integrated circuit comprising:

providing a plurality of levels of conductor, one above the other, each having a plurality of parallel, spaced-apart lines, the conductor in any one of the levels being perpendicular to the conductors in the level below it;

providing vias between selected intersections of the lines in one of the levels and the lines in the level directly below it; and

providing dielectric pillars at every intersection of the lines in one level and the lines at the level below it, where such intersections do not have vias.

12. The method defined by claim 11, including providing a low-k dielectric between the lines in all the levels.

13. A method comprising:

forming a first dielectric layer on first conductors;

forming first openings in the first dielectric layer;

depositing a second dielectric layer on the first dielectric layer so as to fill the first openings;

planarizing the second dielectric layer so as to expose the first dielectric layer and form pillars entirely from the second dielectric layer;

depositing a third dielectric layer on the first dielectric layer;

defining via openings through the first and third dielectric layers exposing underlying first conductors;

forming trenches above the via openings and pillars; and

depositing a conductive material into the via openings and trenches.

14. The method defined by claim 13, wherein the second dielectric layer is harder than the first and third dielectric layers.

15. The method defined by claim 14, including the formation of an etchant stop layer beneath the first dielectric layer.

16. The method defined by claim 14, wherein the first and second dielectric layers are of a lower-k material.

17. A method comprising:

forming a first dielectric layer on a plurality of spaced-apart first conductors;

masking and etching the first dielectric layer so as to form pillars entirely from the first dielectric layer at predetermined locations on the conductors;

forming a second dielectric layer over the pillars and conductors;

opening vias and trenches in the second dielectric, including trenches disposed above the pillars;

forming a barrier layer so as to line the via openings and trenches;

depositing a conductive layer so as to fill the via openings and trenches;

planarizing the surface of the conductive layer to form second conductors; and

forming shunts over the second conductors.

18. The method defined by claim 17, including repeating the steps of claim 17 to form additional levels in an interconnect structure.

19. The method defined by claim 18, including etching away the second dielectric layer after the conductors in the structure have been formed.

20. The method defined by claim 19, wherein the first dielectric layer comprises silicon dioxide.

21. The method defined by claim 19, wherein the first dielectric layer comprises silicon nitride.