Method for manufacturing semiconductor device and apparatus for manufacturing thereof

• US 20050221608A1
• Filed: 05/20/2005
• Published: 10/06/2005
• Est. Priority Date: 08/27/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Souichi Katagiri, Ui Yamaguchi
• Inventors: Katagiri, Souichi, Yamaguchi, Ui
• Granted Patent: US 7,144,298 B2
• Time in Patent Office: Days
• US Class Current: 438/626
• CPC Class Codes: B23H 5/08 Electrolytic grinding
• CPC Class Codes: B24B 37/04 designed for working plane surfaces
• CPC Class Codes: C25F 3/14 locally
• CPC Class Codes: C25F 7/00 Constructional parts, or assemblies thereof, of cells for electrolytic removal of material from objects for both electrolytic coating and removal C25D; Servicing or operating
• CPC Class Codes: H01L 21/32125 by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation

Abstract

The object of the invention is to provide a method of manufacturing a semiconductor device and a processing apparatus for planarization wherein to form copper wiring in multiple layers. The removal of a residue of polishing by local electro polishing, the enhancement of the performance of planarization by using a grindstone and the reduction by small frictional force in electro polishing of damage, are enabled. To achieve the object, the following measures are taken. A residue of polishing of copper is removed by combining the detection of a local area including the residue of polishing of copper and local processing for electro polishing. As small-load processing for planarization is enabled by using electro polishing, multilayer interconnection structure using low-k material as a dielectric interlayer is also enabled. Plural pairs of small unit electrodes in a pair of which minus electrodes surround a plus electrode are provided to a tool for electro polishing, each electrode is connected to a power supply, pulse voltage is applied to each electrode and copper is electrolytically polished.

Claims

1. A processing apparatus for planarization, comprising:

a platen for turning a semiconductor substrate, the platen holding the semiconductor substrate,

a tool for electropolishing, for contacting the semiconductor substrate held by the platen and being turned thereby, and for electrolytically polishing the surface of the substrate,

a power supply for applying voltage to an electrode provided to the tool for electropolishing,

electrolytic solution supplying means for supplying electrolytic solution to the semiconductor substrate, and

an image detector for detecting a polished state of the electrolytically polished surface of the semiconductor substrate, wherein;

the tool for electropolishing is provided with a supporting body where plural pairs of unit electrodes are provided, and in a pair of which electrodes respectively having one pole and another pole, the other pole surrounds the electrode of one pole at a predetermined interval; and

pulse voltage is applied to the electrodes from the power supply.

2. A processing apparatus for planarization according to claim 1, wherein:

the plural pairs of unit electrodes are arrayed linearly or like a beehive at a predetermined interval on the supporting body forming the tool for electropolishing; and

plural grindstones having a height protruded beyond the end of the electrodes are provided to the supporting body.