Test system with differential signal measurement

• US 20050222821A1
• Filed: 03/31/2004
• Published: 10/06/2005
• Est. Priority Date: 03/31/2004
• Status: Active Grant

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Conner, George W.
• Granted Patent: US 7,174,279 B2
• Time in Patent Office: Days
• US Class Current: 702/189
• CPC Class Codes: G01R 31/31708 Analysis of signal quality G01R31/31901 takes precedence; measuring frequencies or analysing frequency spectra per se G01R23/00; measuring non-linear distortion per se G01R23/20
• CPC Class Codes: H04L 1/242 by comparing a transmitted test signal with a locally generated replica

Abstract

A test system with easy to fabricate hardware to make measurements on differential signals. The two legs of a differential signal are applied to a comparator. A variable bias is introduced into the comparison operation. By taking multiple measurements with different bias levels, the level of the differential signal may be determined. The time of measurements relative to the start of the signal can be varied to allow plots of the signal to be made. Variability of the signal caused by noise can be measured by collecting sets of data points with the same bias level at the same relative time. Circuitry for introducing bias into the comparison is disclosed that allows measurements to be made with a pre-packaged, commercially available high speed comparator.

Claims

1. A method of performing a measurement on a differential signal, comprising:

a) providing each leg of the differential signal to an input of a comparator having at least a first and second input;

b) introducing a plurality of bias levels into the comparison, whereby the output of the comparator is a first logical value when the value at the first input exceeds the value at the second input by the bias level;

c) taking a plurality of sets of samples of the output of the comparator, with a set of samples for each of the bias levels, each of the samples in each of the sets correlated in time to a point on the waveform;

d) selecting a set of samples having values with a predetermined percentage of a predetermined logical value; and

e) associating the bias value used to take the samples in the selected set with the value of the differential signal at the point on the waveform.

2. The method of claim 1 wherein introducing a bias level comprises passing a current through a resistor connected to one of the first and second inputs of the comparator.

3. The method of claim 2 wherein introducing a plurality of bias level comprises passing a first current through a first resistor connected to the first input of the comparator and passing a second current through a second resistor connected to the second input of the comparator, with the plurality of bias levels introduced by altering the relative level of the first current and the second current.

4. The method of claim 2 wherein the comparator is contained inside a commercially available component having leads accessible at its exterior, including exterior leads coupled to the first and second inputs of the comparator.

5. The method of claim 4 wherein the resistor is outside the commercially available component and coupled to an input of the comparator.

6. The method of claim 2 wherein each leg of the differential signal is AC coupled to one of the first and second inputs to the comparator.

7. The method of claim 1 wherein introducing a bias level comprises altering the operating characteristics of the comparator.

8. The method of claim 1 wherein the comparator is contained inside a commercially available component having leads accessible at its exterior, including exterior leads coupled to the first and second inputs of the comparator and introducing a bias level comprises applying an electrical signal to at least one of the leads coupled to the first and second inputs of the comparator.

9. The method of claim 1 wherein the differential signal has a plurality of rising edges and taking samples correlated in time to a point in the waveform comprises setting strobe times at which the comparator takes samples to be at a predetermined time relative to the start of a rising edge.

10. A method of manufacturing a semiconductor component incorporating the method of claim 1 wherein the differential signal is an output of the semiconductor component at a stage in its manufacture and steps b) through e) of claim 1 are repeated to associate values with a plurality of points on the differential signal.

11. The method of claim 10 wherein the values associated with the plurality of points on the differential signals are used to analyze the performance of the semiconductor component and subsequent steps in the manufacturing process of the semiconductor component are selected in response to the analysis.

12. A process of making semiconductor devices using the method of claim 1, the process comprising:

a) connecting a semiconductor device under test to a test system;

b) stimulating the device under test with signals from the test system;

c) providing a differential signal generated by the device under test to the test system and performing, with the test system, the steps of claim 1 to provide parameters of the differential signal;

d) using the parameters of the differential signal to adjust the manufacturing process for making semiconductor devices.

13. The process of making semiconductor devices of claim 12 wherein adjusting the manufacturing process comprises speed binning the device under test.

14. An automatic test system suitable for making measurements of a differential signal applied as an input to the test system, the test system having a measurement circuit comprising:

a) a comparator having;

i) a first and second signal input terminals

ii) an output providing a logical signal indicating the results of a comparison; and

iii) a timing input controlling the time at which a comparison is made;

b) means for biasing the comparison by a variable amount in response to a control signal;

c) control circuitry providing a timing signal connected to the timing input of the comparator and a control signal to the means for biasing; and

d) data analysis circuitry having an input coupled to the output of the comparator, the data analysis circuitry determining parameters of the differential signal from the output of the comparator.

15. The automatic test system of claim 14 wherein the input terminals of the comparator are AC coupled to the input of the test system and the means for biasing the comparison comprises at least one voltage source coupled to at least one of the first and second input terminals of the comparator.

16. The automatic test system of claim 15 wherein the voltage source comprises a current source and a resistor with the resistor connected to the current source and an input terminal of the comparator.

17. The automatic test system of claim 15 wherein the comparator is enclosed in semiconductor packaging with the first and second input terminals accessible through leads on the outside of the package.

18. The automatic test system of claim 17 wherein the comparator is part of a commercially available semiconductor component,

19. The automatic test system of claim 18 wherein the commercially available semiconductor component comprises a differential receiver.

20. The automatic test system of claim 19 wherein the commercially available semiconductor component comprises a Gigabit receiver.

21. The automatic test system of claim 14 wherein the comparator is a portion of an instrument installed in the automatic test system.

22. The automatic test system of claim 14 wherein the test system includes the timing generator and the control circuitry comprises the timing generator.

23. The automatic test system of claim 14 wherein the data analysis circuit comprises a general purpose computer programmed to determine parameters of the differential signal.

24. The automatic test system of claim 23 wherein the data analysis circuit comprises a user interface through which the eye pattern of the differential signal is displayed.