System and method for controlling DMA data transfer

• US 20050223136A1
• Filed: 06/01/2005
• Published: 10/06/2005
• Est. Priority Date: 03/05/2003
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tanaka, Ryuta, Tsuruta, Toru, Tanaka, Ritsuko, Kumamoto, Norichika
• Granted Patent: US 7,415,550 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A data transfer control system that can change the way of DMA transfers to meet the requirements of each application. The data transfer control system includes a DMA controller (DMAC) and a DMAC memory dedicated for DMA control purposes. The DMAC performs DMA transfers according to a DMA program stored in the DMAC memory. Each time a new DMA request is received, the DMAC saves its parameters in a DMA request parameter table, and each DMA request parameter table is registered with a DMA request management table. In this way, the received DMA requests are queued in the DMA request management table. They are executed in a first-in first-out fashion. The progress of ongoing DMA transfers are managed in a DMA channel status table disposed for each DMA channel.

Claims

1. A data transfer control system for transferring data between memory areas, comprising:

a direct memory access (DMA) controller memory storing a DMA program describing how to perform a DMA transfer; and

a DMA controller that performs, in response to a DMA request, a DMA transfer between specified memory areas according to the DMA program stored in said DMA controller memory.

2. The data transfer control system according to claim 1, further comprising a dedicated bus connecting said DMA controller with said DMA controller memory.

3. The data transfer control system according to claim 1, wherein said DMA controller comprises:

an instruction decoder circuit that decodes instructions contained in the DMA program; and

an address generator circuit that produces memory addresses for data transfer operations.

4. The data transfer control system according to claim 1, wherein:

said DMA controller stores specified DMA parameters in said DMA controller memory each time a new DMA request is received, and sequentially executes requested data transfers while reading out the DMA parameters from said DMA controller memory.

5. The data transfer control system according to claim 1, wherein:

said DMA controller provides a plurality of channels each accepting DMA requests;

DMA requests directed to each channel are stored in said DMA controller memory; and

said DMA controller executes the DMA requests stored in said DMA controller memory by switching from one channel to another channel each time a unit amount of data has been transferred according to one of the DMA requests.

6. The data transfer control system according to claim 1, wherein:

the DMA request contains address parameters and a mode parameter; and

said DMA controller determines whether to recognize the address parameters as absolute addresses or relative addresses, based on the mode parameter.

7. The data transfer control system according to claim 1, wherein:

the DMA request specifies a rectangular area in a source memory space; and

said DMA controller transfers data in the rectangular area that is extracted from the source memory space in response to the DMA, request.

8. The data transfer control system according to claim 7, wherein:

the rectangular area is divided into a plurality of segments with discontinuous addresses; and

said DMA controller transfers the rectangular area, skipping from one segment to another segment by generating the discontinuous addresses.

9. The data transfer control system according to claim 7, wherein the rectangular area is part of image data.

10. The data transfer control system according to claim 7, wherein said DMA controller interprets the DMA request as a transfer request for a rectangular area or a continuous memory block, depending on a mode parameter specified in the DMA request.

11. The data transfer control system according to claim 1, further comprising a host processor to control said DMA controller.

12. The data transfer control system according to claim 11, wherein said host processor are connected to said DMA controller via dedicated signal lines.

13. The data transfer control system according to claim 1, wherein said DMA controller comprises:

an instruction decoder that reads each instruction of the DMA program from said DMA controller memory and decodes the instruction to produce control signals; and

an address generator circuit that generates DMA addresses according to the control signals from said instruction decoder.

14. A direct memory access (DMA) controller for controlling DMA transfers, comprising:

an instruction decoder that reads each instruction of a DMA program from a DMA controller memory and decodes the instruction to produce control signals; and

an address generator circuit that generates DMA addresses according to the control signals from said instruction decoder.

15. A method for controlling direct memory access (DMA) transfers, comprising the steps of:

providing a dedicated memory for DMA control purposes, the dedicated memory storing a DMA program that describes how to perform a DMA transfer; and

performing, in response to a DMA request, a DMA transfer between specified memory areas according to the DMA program stored in said DMA controller memory.