Semiconductor memory device and method of outputting data signals

• US 20050223152A1
• Filed: 03/28/2005
• Published: 10/06/2005
• Est. Priority Date: 03/30/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Sugawara, Hiroshi
• Granted Patent: US 7,243,180 B2
• Time in Patent Office: Days
• US Class Current: 710/316
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A semiconductor memory device includes first to third data buses, a first connection circuit and a second connection circuit. The first connection circuit is provided between the first data bus and the second data bus, inverts and transfers a first output signal on the first data bus read out from a memory section onto the second data bus in response to a first selection signal, inverts and transfers a second output signal on the second data bus read out from the memory section onto the first data bus in response to a second selection signal, and connects the first data bus and the second data bus in response to a reset signal. The second connection circuit is provided between the second data bus and the third data bus, inverts and transfers the inverted first output signal on the second data bus onto the third data bus in response to the first selection signal and transfers the second output signal on the second data bus onto the third data bus in response to the second selection signal.

Claims

1. A semiconductor memory device comprising:

first to third data buses;

a first connection circuit provided between said first data bus and said second data bus, to invert and transfer a first output signal on said first data bus read out from a memory section onto said second data bus in response to a first selection signal, to invert and transfer a second output signal on said second data bus read out from said memory section onto said first data bus in response to a second selection signal, and to connect said first data bus and said second data bus in response to a reset signal; and

a second connection circuit provided between said second data bus and said third data bus, to invert and transfer the inverted first output signal on said second data bus onto said third data bus in response to said first selection signal and to transfer said second output signal on said second data bus onto said third data bus in response to said second selection signal.

2. The semiconductor memory device according to claim 1, wherein a length of said first data bus is substantially equal to that of said second data bus.

3. The semiconductor memory device according to claim 1, further comprising:

a first sense amplifier section configured to amplify and output a signal read out from said memory section onto said first data bus as said first output signal in response to said first selection signal; and

a second sense amplifier section configured to amplify and output a signal read out from said memory section onto said second data bus as said second output signal in response to said second selection signal.

4. The semiconductor memory device according to claim 3, wherein when one of the output of said first sense amplifier section and the output of said second sense amplifier section is effective, the other is not effective.

5. The semiconductor memory device according to claim 3, wherein a bus length between said third data bus and said first sense amplifier section is longer than a bus length between said third data bus and said second sense amplifier section.

6. The semiconductor memory device according to claim 3, wherein said first sense amplifier section and said first data bus are provided in a first area of a chip area,

said second sense amplifier section and said second data bus are provided in a second area of the chip area, and

said first connection circuit is provided in a third area of the chip area between said first area and said second area.

7. The semiconductor memory device according to claim 6, wherein said first sense amplifier section and said first data bus are provided in a first area of a chip area,

said third data bus and said bus driver circuit are provided in a second area of the chip area, and

said second sense amplifier section and said second data bus are provided in a third area of the chip area between said first area of the chip area and said second area of the chip area, and

said first connection circuit is provided in a fourth area of the chip area between said first area and said third area.

8. The semiconductor memory device according to claim 1, wherein said first connection circuit comprises:

an inverting unit provided between said first data bus and said second data bus, to invert and transfer said first output signal on said first data bus onto said second data bus in response to said first selection signal, to invert and transfer said second output signal on said second data bus onto said first data bus in response to said second selection signal; and

an equalizing circuit configured to connect said first data bus and said second data bus in response to said reset signal.

9. The semiconductor memory device according to claim 8, wherein said equalizing circuit comprises:

a transfer gate in which one of terminals is connected with said first data bus and the other terminal is connected with said second data bus, and

said reset signal is supplied directly to one of two gates of said transfer gate, and said reset signal is supplied to the other gate of said transfer gate through an inverter.

10. The semiconductor memory device according to claim 1, wherein said second connection circuit comprises:

a first buffer section configured to invert and transfer the inverted first output signal on said second data bus onto said third data bus in response to said first selection signal; and

a second buffer section configured to transfer said second output signal on said second data bus onto said third data bus in response to said second selection signal.

11. The semiconductor memory device according to claim 1, further comprising:

a control circuit configured to generate said first selection signal or said second selection signal, and said reset signal alternately.

12. A method of outputting data signals in a semiconductor memory device, comprising:

sensing a signal read out from a memory section to output onto a first data bus as a first output signal in response to a first selection signal;

inverting and transferring said first output signal on said first data bus onto a second data bus in response to said first selection signal;

inverting and transferring the inverted first output signal on said second data bus onto a third data bus in response to said first selection signal; and

connecting said first data bus and said second data bus in response to a reset signal to equalize voltages of said first and second data buses.

13. The method according to claim 12, further comprising:

sensing a signal read out from said memory section to output onto said second data bus as a second output signal in response to a second selection signal;

transferring said second output signal on said second data bus onto said first data bus and said third bus in response to said second selection signal; and

connecting said first data bus and said second data bus in response to said reset signal to equalize voltages of said first and second data buses.

14. The method according to claim 12, wherein a length of said first data bus is substantially equal to that of said second data bus.

15. The method according to claim 12, further comprising:

generating said first selection signal or said second selection signal, and said reset signal alternately.

16. A semiconductor memory device comprising:

an inverting section provided between an output of a first sense amplifier section and an output of a second sense amplifier section, and configured to invert the output of said first sense amplifier section;

an equalizing circuit configured to couple the output of said first sense amplifier section and an output of said inverting section in a predetermined period;

a common bus;

a bus driver circuit configured to transfer one of an output of said inverting section and the output of said second sense amplifier section on said common bus onto an output bus with inversion or no inversion of the one output.

17. The semiconductor memory device according to claim 16, wherein said bus driver circuit inverts the output of said inverting section and outputs the inverted output onto said output bus, and outputs the output of said second sense amplifier section onto said output bus with no inversion.

18. The semiconductor memory device according to claim 16, wherein when one of the output of said first sense amplifier section and the output of said second sense amplifier section is effective, the other is not effective.

19. The semiconductor memory device according to claim 16, wherein a distance between said common bus and said first sense amplifier section is longer than the distance between said common bus and said second sense amplifier section.