Memory hub and access method having internal row caching
First Claim
1. A memory module, comprising:
- a plurality of memory devices; and
a memory hub, comprising;
a link interface receiving memory requests for access to a row of memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to a row of memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests, at least some of the memory requests coupled to the memory devices being responsive to memory requests transferred from the link interface to the memory device interface;
a row cache memory coupled to the memory device interface for receiving and storing read data from a row of memory cells being accessed responsive to at least one of the memory requests being coupled from the memory device interface to the at least one memory device; and
a sequencer coupled to the link interface and the memory device interface and the row cache memory, the sequencer being operable to generate and couple to the memory device interface memory requests to read data from memory cells in row of memory cells being accessed, the read data read from the memory cells in the row of memory cells being accessed being stored in the row cache memory.
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Accused Products
Abstract
A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices. The memory hub includes a row cache memory that stores data as they are read from the memory devices. When the memory module is not being accessed by the controller, a sequencer in the memory module generates requests to read data from a row of memory cells. The data read responsive to the generated read requests are also stored in the row cache memory. As a result, read data in the row being accessed may be stored in the row cache memory even though the data was not previously read from the memory device responsive to a memory request from the controller.
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Citations
45 Claims
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1. A memory module, comprising:
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a plurality of memory devices; and
a memory hub, comprising;
a link interface receiving memory requests for access to a row of memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to a row of memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests, at least some of the memory requests coupled to the memory devices being responsive to memory requests transferred from the link interface to the memory device interface;
a row cache memory coupled to the memory device interface for receiving and storing read data from a row of memory cells being accessed responsive to at least one of the memory requests being coupled from the memory device interface to the at least one memory device; and
a sequencer coupled to the link interface and the memory device interface and the row cache memory, the sequencer being operable to generate and couple to the memory device interface memory requests to read data from memory cells in row of memory cells being accessed, the read data read from the memory cells in the row of memory cells being accessed being stored in the row cache memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory module, comprising:
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a plurality of memory devices; and
a memory hub, comprising;
a link interface receiving memory requests for access to a row of memory cells in at least one of the memory devices;
a memory device interface coupled to the memory devices, the memory device interface being operable to couple memory requests to the memory devices for access to a row of memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests, at least some of the memory requests coupled to the memory devices being responsive to memory requests transferred from the link interface to the memory device interface;
a sequencer coupled to the link interface and the memory device interface and the row cache memory, the sequencer being operable to output an address contained in each read memory request received from the link interface;
a row cache memory coupled to the memory device interface for receiving and storing read data from a row of memory cells being accessed responsive to one of the memory requests being coupled from the memory device interface to the at least one memory device, the row cache memory further being operable to receive the addresses from the sequencer to determine if data called for by the memory request is stored in the row cache memory, the row cache memory outputting the read data and generating a hit signal if the data called for by the memory request is stored in the row cache memory and generating a row miss signal if the data called for by the memory request is not stored in the row cache memory; and
a multiplexer having data inputs coupled to the row cache memory and to the memory device interface, a data output coupled to the link interface and a control input coupled to receive the row cache hit and row cache miss signals from the row cache memory, the multiplexer coupling read data from the memory device interface responsive to the row cache miss signal and coupling read data from the row cache memory responsive to the row cache hit signal. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A memory hub, comprising:
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a link interface receiving memory requests, at least some of the memory requests including a row address;
a memory device interface operable to output memory requests and to receive read data responsive to at least some of the memory requests, at least some of the memory requests output by the memory device interface being responsive to memory requests transferred from the link interface to the memory device interface;
a row cache memory coupled to the memory device interface for receiving and storing read data received from the memory device interface responsive to at least one of the memory requests being output from the memory device interface; and
a sequencer coupled to the link interface and the memory device interface and the row cache memory, the sequencer being operable to generate and couple to the memory device interface memory requests to read data associated with read data received by the memory device interface responsive to memory requests transferred from the link interface to the memory device interface, the read data read received responsive to memory requests from the sequencer being stored in the row cache memory. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24-41. -41. (canceled)
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42. A method of reading data in each of a plurality of memory modules using a controller coupled to the memory modules, the method comprising:
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receiving memory requests from the controller by a first one of the memory modules, at least one of the memory requests being a request to access memory cells in a row of memory cells of at least one memory device in a plurality of memory devices included in the first memory module;
coupling the received memory requests to the at least one memory device in the first memory module;
generating requests to read data from memory cells in the row of memory cells being accessed responsive to the request to access memory cells in a row of memory cells of the at least one memory device, the requests being generated when memory requests from the controller are not being coupled to the at least one memory device;
coupling the generated memory requests to the at least one memory device; and
storing in cache memory in the first memory module read data responsive to received memory requests and the generated memory requests. - View Dependent Claims (43, 44, 45)
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Specification