User-configurable pre-recorded memory

• US 20050223182A1
• Filed: 01/15/2005
• Published: 10/06/2005
• Est. Priority Date: 04/04/2004
• Status: Abandoned Application

• Current Assignee: Guobiao Zhang
• Original Assignee: Guobiao Zhang
• Inventors: Zhang, Guobiao
• Application Number:
  US11/036,448
• Publication Number:
  US 20050223182A1
• Time in Patent Office: Days
• US Class Current: 711/163
• CPC Class Codes: G06F 21/10 Protecting distributed programs or content, e.g. vending or licensing of copyrighted material protection in video systems or pay television H04N7/16 ; Digital rights management [DRM]
• CPC Class Codes: G06F 21/62 Protecting access to data via a platform, e.g. using keys or access control rules
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence

Abstract

In a user-configurable pre-recorded memory (IC-PM), a user can select the files he wishes to access and therefore, only pay the copyright fees for the selected files. Three-dimensional memory (3D-M)-based UC-PM offers low cost and large capacity. More importantly, it provides impenetrable copyright protection and will enable a copyright distribution model, fair to both copyright owners and consumers.

Claims

1. A user-configurable pre-recorded memory, comprising:

a pre-recorded memory storing a plurality of pre-recorded files; and

an access control block controlling access to each of said pre-recorded files.

2. The user-configurable pre-recorded memory according to claim 1, wherein said access control block further comprises an access tag block, said access tag block containing accessibility information for said pre-recorded files.

3. The user-configurable pre-recorded memory according to claim 2, wherein said accessibility information contains an accessibility bit or the remaining number of allowed accesses.

4. The user-configurable pre-recorded memory according to claim 2, wherein said access control block further comprises an access configuration block, said access configuration block configuring said access tag based on an inputted access code.

5. The user-configurable pre-recorded memory according to claim 4, wherein said access configuration block further comprises a code-conversion table, said code-conversion table further comprising a plurality of access codes and the associated file index/access levels.

6. The user-configurable pre-recorded memory according to claim 4, wherein said access configuration block further comprises an access-extraction engine.

7. The user-configurable pre-recorded memory according to claim 1, wherein said access control block further comprises a chip ID.

8. The user-configurable pre-recorded memory according to claim 1, further comprising an electrically programmable memory for storing a chip ID or a plurality of access codes.

9. The user-configurable pre-recorded memory according to claim 1, wherein:

said pre-recorded memory is a three-dimensional memory (3D-M); and

said user-configurable pre-recorded memory further comprises a substrate circuit underneath said 3D-M.

10. The user-configurable pre-recorded memory according to claim 9, wherein said access control block is a portion of said substrate circuit.

11. The user-configurable pre-recorded memory according to claim 9, wherein

at least a portion of said pre-recorded files are encrypted;

and

said substrate circuit further comprises a decryption engine.

12. The user-configurable pre-recorded memory according to claim 9, wherein said substrate circuit further comprises a digital-to-analog converter.

13. The user-configurable pre-recorded memory according to claim 12, wherein said digital-to-analog converter is a pulse-width modulation converter.

14. A three-dimensional memory with integrated pulse-width modulation (PWM) converter, comprising:

a substrate circuit comprising a PWM converter;

a three-dimensional memory (3D-M) array stacked on top of said substrate circuit, said PWM converter located underneath said 3D-M array; and

a plurality of inter-level vias connecting said 3D-M array with said substrate circuit.

15. The three-dimensional memory with integrated PWM converter according to claim 14, wherein said substrate circuit further comprises a circuit block selected from a group consisting of access control block, decryption engine, signal processor and digital-to-analog converter.

16. A diode-based memory, comprising:

a substrate with a plurality of functional transistors formed thereon; and

a diode-based memory array comprising a plurality of diode-based memory cells and address-selection lines.

17. The diode-based memory according to claim 16, wherein said diode-based memory array is a three-dimensional memory (3D-M) array;

and

said functional transistors are located underneath said 3D-M array.

18. The diode-based memory according to claim 16, wherein the minimum poly gate pitch of said functional transistors is larger than the minimum line pitch of said address-selection lines.

19. The diode-based memory according to claim 16, further comprising at least one diode-based memory unit array, said unit array further comprising a plurality of word lines and bit lines, a single word line providing current to selected ones of said bit lines during read-out, wherein

said word line is wider than said bit line;

and/or

said word line has a lower sheet rho than said bit line.

20. The diode-based memory according to claim 19, wherein

said word line is thicker than said bit line;

and/or

said word line comprises a material more conductive than said bit line.