Device-level address translation within a programmable non-volatile memory device

• US 20050223186A1
• Filed: 03/25/2005
• Published: 10/06/2005
• Est. Priority Date: 03/25/2004
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Riverstone Networks, Inc.
• Inventors: Balakrishnan, Thirumalpathy, Belevich, Artem
• Granted Patent: US 7,222,214 B2
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10

Abstract

A programmable non-volatile memory device includes block switching logic that enables device-level translation rules to be changed. The device-level translation rules map the external addresses received by the flash memory device to the internal addresses of the programmable non-volatile memory device. Because the device-level translation rules are changeable, the physical location in the programmable non-volatile memory device to which an external address maps can be changed in a manner that is transparent to off-device operations. By allowing device-level translation rules to be changed, block management functions can be accomplished within the programmable non-volatile memory device itself.

Claims

1. A programmable non-volatile memory device comprising:

programmable non-volatile memory having blocks that are identified by internal addresses;

an address bus interface configured to receive external addresses as part of read and write operations; and

block switching logic operatively associated with the programmable non-volatile memory and the address bus interface and configured to enable a translation rule that applies to an external address to be changed from a first translation rule that maps the external address to a first internal address to a second translation rule that maps the external address to a second internal address.

2. The programmable non-volatile memory device of claim 1 wherein the block switching logic includes a programming interface configured to enable changing from the first translation rule to the second translation rule.

3. The programmable non-volatile memory device of claim 1 wherein the block switching logic includes a switching cell that includes a portion of the programmable non-volatile memory.

4. The programmable non-volatile memory device of claim 1 wherein the block switching logic is configured to produce a non-volatile change from the first translation rule to the second translation rule.

5. The programmable non-volatile memory device of claim 1 wherein the block switching logic includes means for atomically switching from the first translation rule to the second translation rule.

6. The programmable non-volatile memory device of claim 5 wherein the means for atomically switching comprises at least one non-volatile selection bit.

7. The programmable non-volatile memory device of claim 1 wherein the block switching logic includes multiple different translation maps, and wherein the block switching logic is configured to utilize only one of the multiple translation maps at any one time.

8. The programmable non-volatile memory device of claim 1 wherein the block switching logic includes a translation map that includes multiple changeable translation rules.

9. The programmable non-volatile memory device of claim 1 wherein the block switching logic includes a portion of the programmable non-volatile memory to store at least two translation maps.

10. A method for performing read and write operations in a programmable non-volatile memory device, wherein memory addresses for read and write operations are identified external to the programmable non-volatile memory device by external addresses and internal to the programmable non-volatile memory device by internal addresses, the method comprising:

receiving a first instance of an external address at the programmable non-volatile memory device;

within the programmable non-volatile memory device, translating the first instance of the external address to a first internal address according to a first translation rule;

after the first instance of the external address has been received and translated, changing the translation rule that applies to the external address from the first translation rule to a second translation rule;

receiving a second instance of the external address at the programmable non-volatile memory device; and

within the programmable non-volatile memory device, translating the second instance of the external address to a second internal address according to the second translation rule.

11. The method of claim 10 wherein the translation rule that applies to the external address is changed by switching at least one selection bit within the programmable non-volatile memory device.

12. The method of claim 11 wherein the change of the at least one selection bit is a non-volatile change.

13. The method of claim 10 wherein the change in translation rules is non-volatile.

14. The method of claim 10 wherein changing the translation rule comprises making a non-volatile change within the programmable non-volatile memory device.

15. The method of claim 10 wherein the translation rule that applies to the external address is changed atomically from the first translation rule to the second translation rule.

16. The method of claim 10 further comprising atomically changing from a first set of translation rules to a second set of translation rules.

17. A method for performing a firmware upgrade in an embedded system that includes a programmable non-volatile memory device, wherein memory addresses for read and write operations are identified external to the programmable non-volatile memory device by external addresses and internal to the programmable non-volatile memory device by internal addresses, the method comprising:

applying a first translation rule to an external address, wherein the first translation rule maps the external address to a first internal address of the programmable non-volatile memory device and wherein a first set of computer code is stored at the first internal address;

writing a second set of computer code to the programmable non-volatile memory device at a second internal address, wherein the second set of computer code is an updated version of the first set of computer code;

after the second set of computer code is written to the programmable non-volatile device at the second internal address, changing the translation rule that applies to the external address, the translation rule that applies to the external address being changed to a second translation rule that maps the external address to the second internal address.

18. The method of claim 17 wherein changing the translation rule that applies to the external address comprises making a non-volatile change within the programmable non-volatile memory device.

19. The method of claim 17 wherein changing the translation rule that applies to the external address comprises atomically changing from the first translation rule to the second translation rule.

20. The method of claim 17 further including erasing the memory at the second internal address before the second set of computer code is written.