SEMICONDUCTOR EMBEDDED MEMORY DEVICES HAVING BIST CIRCUIT SITUATED UNDER THE BONDING PADS
First Claim
1. An embedded memory chip, comprising:
- a logic circuit;
a memory unit coupled to said logic circuit, wherein said logic circuit and said memory unit are fabricated substantially in a center area of said embedded memory chip;
a plurality of bonding pads situated on a peripheral area adjacent to said center area of said embedded memory chip; and
a built-in self test (BIST) circuit situated under at least one of said bonding pads for detecting faults in said embedded memory chip.
1 Assignment
0 Petitions
Accused Products
Abstract
An embedded memory chip having BIST (built-in self test) circuit under pad is disclosed. The embedded memory chip includes a logic circuit and a memory unit coupled to the logic circuit. The logic circuit and memory unit are fabricated substantially in a center area of the embedded memory chip. A number of bonding pads are situated on a peripheral area adjacent to the center area of the embedded memory chip. The BIST circuit is situated directly under at least one of the bonding pads. The BIST circuit is activated when implementing an IC testing on the embedded memory chip for detecting faults in the memory unit and is deactivated as a disuse part of the embedded memory chip after finishing the IC testing.
11 Citations
20 Claims
-
1. An embedded memory chip, comprising:
-
a logic circuit;
a memory unit coupled to said logic circuit, wherein said logic circuit and said memory unit are fabricated substantially in a center area of said embedded memory chip;
a plurality of bonding pads situated on a peripheral area adjacent to said center area of said embedded memory chip; and
a built-in self test (BIST) circuit situated under at least one of said bonding pads for detecting faults in said embedded memory chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
-
-
11. An embedded memory chip, comprising:
-
a logic circuit;
a memory unit coupled to said logic circuit, wherein said logic circuit and said memory unit are fabricated substantially in a center area of said embedded memory chip;
a plurality of bonding pads situated on a peripheral area adjacent to said center area of said embedded memory chip; and
a built-in self test (BIST) circuit situated under at least one of said bonding pads, wherein said BIST circuit is activated when implementing an IC testing on said embedded memory chip for detecting faults in said memory unit and is deactivated as a disuse part of said embedded memory chip after finishing said IC testing. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
-
Specification