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SEMICONDUCTOR EMBEDDED MEMORY DEVICES HAVING BIST CIRCUIT SITUATED UNDER THE BONDING PADS

  • US 20050223289A1
  • Filed: 03/24/2004
  • Published: 10/06/2005
  • Est. Priority Date: 03/24/2004
  • Status: Abandoned Application
First Claim
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1. An embedded memory chip, comprising:

  • a logic circuit;

    a memory unit coupled to said logic circuit, wherein said logic circuit and said memory unit are fabricated substantially in a center area of said embedded memory chip;

    a plurality of bonding pads situated on a peripheral area adjacent to said center area of said embedded memory chip; and

    a built-in self test (BIST) circuit situated under at least one of said bonding pads for detecting faults in said embedded memory chip.

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