Method and system for fabricating integrated circuit chips with unique identification numbers

• US 20050224590A1
• Filed: 04/13/2005
• Published: 10/13/2005
• Est. Priority Date: 04/13/2004
• Status: Abandoned Application

• Current Assignee: University of Maryland
• Original Assignee: University of Maryland
• Inventors: Bandy, William R., Melngailis, John
• Application Number:
  US11/104,517
• Publication Number:
  US 20050224590A1
• Time in Patent Office: Days
• US Class Current: 235/492
• CPC Class Codes: G06K 1/126 by photographic or thermographic registration recording apparatus for measuring instruments G01D15/00

Abstract

A method, system, and apparatus for writing data to integrated circuits is described. A charged particle source supplies a beam of charged particles. A wafer plate mounts a wafer having a plurality of transistors distributed among an array of integrated circuits on a surface. A beam column receives the beam of charged particles and selectively passes the beam of charged particles to the surface of the wafer. The selectively passed beam of charged particles irradiates selected transistors of the plurality of transistors to cause the selected transistors to permanently change from a first state to a second state. The second state can be a fully “on” state, a fully “off” state, or a state in between for the selected transistors. Each integrated circuit of the array includes at least one of the selected transistors and at least one non-selected transistor. A combination of selected and non-selected transistors of the integrated circuit corresponds to data for the integrated circuit.

Claims

1. An system for writing data to integrated circuit (IC) chips of a wafer, comprising:

a charged particle source that supplies a beam of charged particles;

a beam column; and

a wafer plate that mounts a wafer having an array of integrated circuits each including a plurality of transistors;

wherein the beam column receives the beam of charged particles and selectively passes the beam of charged particles to the surface of the wafer;

wherein the selectively passed beam of charged particles irradiates selected transistors of said plurality of transistors to cause said selected transistors to each permanently enter a desired state,

wherein said plurality of transistors for each integrated circuit of said array includes at least one of said selected transistors, wherein a combination of states of said plurality of transistors of an integrated circuit corresponds to data for said integrated circuit.

2. The system of claim 1, wherein said beam of charged particles irradiates a channel region of said selected transistors to alter current flow capability through said channel region.

3. The system of claim 1, wherein said charged particles are electrons.

4. The system of claim 1, wherein said charged particles are ions.

5. The system of claim 4, wherein said beam of ions implants ions in a channel region of said selected transistors to alter current flow capability through said channel region.

6. The system of claim 4, wherein said beam column focuses said beam of ions at the surface of the wafer.

7. The system of claim 4, wherein said beam of ions passes through a single aperture.

8. The system of claim 7, wherein at a particular time, said beam column aims said beam at a particular transistor of said selected transistors.

9. The system of claim 7, wherein said aperture is rounded.

10. The system of claim 7, wherein said aperture is rectangular.

11. The system of claim 4, further comprising a mask having a plurality of apertures, wherein said beam of ions passes through said plurality of apertures to create a plurality of separate sub-beams of ions that irradiate the selected transistors.

12. The system of claim 11, wherein at a particular time, said beam column positions said beam of ions such that said plurality of separate sub-beams of ions irradiate a plurality of transistors of said selected transistors.

13. The system of claim 4, wherein said beam column selectively passes said beam and blanks said beam.

14. The system of claim 4, further comprising a computer system that receives position information regarding the wafer.

15. The system of claim 14, further comprising a position sensor that detects a position of said wafer and generates said position information.

16. The system of claim 15, wherein said position sensor is a laser interferometer.

17. The system of claim 14, wherein said computer system provides a position control signal to said wafer stage to control a position of said wafer.

18. The system of claim 17, wherein said wafer stage moves said wafer in a serpentine fashion so that all selected transistors on the surface of the wafer are moved through a target area of said beam.

19. The system of claim 14, wherein said computer system provides a control signal to said beam column to cause said beam column to selectively pass or blank said beam.

20. The system of claim 1, wherein the desired state for a particular selected transistor is an on state.

21. The system of claim 1, wherein the desired state for a particular selected transistor is an off state.

22. The system of claim 1, wherein the desired state for a particular selected transistor is a state between an on state and an off state.

23. A method for writing data to an (IC) chip having a plurality of transistors, comprising:

generating a beam of charged particles; and

directing the beam at a transistor of the IC chip, comprising the step of implanting charged particles of the beam in the transistor to cause current flow through the transistor during operation of the transistor to be altered to cause the transistor to permanently enter a desired state.

24. The method of claim 23, wherein said implanting step comprises:

implanting charged particles of the beam in a channel region of the transistor to cause current flow through the channel region of the transistor to be altered during operation of the transistor.

25. The method of claim 23, wherein the charged particles are electrons, wherein said generating step comprises generating a beam of electrons.

26. The method of claim 23, wherein the charged particles are ions, wherein said generating step comprises generating a beam of ions.

27. The method of claim 26, wherein said implanting step comprises implanting ions in a channel region of the transistor to alter current flow capability through the channel region.

28. The method of claim 23, further comprising:

focusing the beam at the surface of the wafer.

29. The method of claim 26, further comprising:

passing the beam of ions through a single aperture.

30. The method of claim 26, further comprising:

passing the beam of ions through a mask having a plurality of apertures to create a plurality of separate sub-beams of ions.

31. The method of claim 30, wherein said directing step comprises positioning the beam of ions such that the plurality of separate sub-beams of ions simultaneously irradiate a plurality of transistors of the IC chip.

32. The method of claim 26, further comprising:

selectively blanking the beam.

33. The method of claim 26, wherein a combination of the transistor and at least one further transistor of the IC chip corresponds to a data string for the IC chip.

34. A method for writing data to integrated circuits of a wafer, comprising:

generating a beam of charged particles; and

directing the beam at a wafer having a surface comprising an array of integrated circuits each having a plurality of transistors, comprising the step of implanting charged particles of the beam in selected transistors of the plurality of transistors to cause the selected transistors to each permanently enter a desired state;

wherein the plurality of transistors of each integrated circuit of the array includes at least one of the selected transistors, wherein a combination of states of the plurality of transistors of an integrated circuit corresponds to data for the integrated circuit.

35. The method of claim 34, wherein said implanting step comprises:

implanting charged particles of the beam in a channel region of the selected transistors to cause current flow through the channel region of the selected transistors to be altered during operation of the selected transistors.

36. The method of claim 34, wherein the charged particles are electrons, wherein said generating step comprises generating a beam of electrons.

37. The method of claim 34, wherein the charged particles are ions, wherein said generating step comprises generating a beam of ions.

38. The method of claim 37, wherein said implanting step comprises implanting ions in a channel region of the selected transistors to alter current flow capability through the channel region.

39. The method of claim 34, further comprising:

focusing the beam at the surface of the wafer.

40. The method of claim 37, further comprising:

passing the beam of ions through a single aperture.

41. The method of claim 37, further comprising:

passing the beam of ions through a mask having a plurality of apertures to create a plurality of separate sub-beams of ions.

42. The method of claim 41, wherein said directing step comprises positioning the beam of ions such that the plurality of separate sub-beams of ions simultaneously implant a plurality of the selected transistors during said implanting step.

43. The method of claim 34, further comprising:

selectively blanking the beam.

44. The method of claim 34, further comprising:

receiving position information regarding the wafer.

45. The method of claim 44, further comprising:

detecting a position of the wafer; and

generating the position information.

46. The method of claim 45, further comprising:

providing a position control signal to the wafer stage to control a position of the wafer based on the position information.

47. The method of claim 46, further comprising:

moving the wafer in a serpentine fashion so that all selected transistors on the surface of the wafer are moved through a target area of the beam.