Ultra low-cost uncooled infrared detector arrays in CMOS

• US 20050224714A1
• Filed: 04/06/2005
• Published: 10/13/2005
• Est. Priority Date: 04/08/2004
• Status: Abandoned Application

• Current Assignee: Tayfun Akin
• Original Assignee: Tayfun Akin
• Inventors: Eminoglu, Selim, Akin, Tayfun, Tanrikulu, M. Yusuf
• Application Number:
  US11/100,037
• Publication Number:
  US 20050224714A1
• Time in Patent Office: Days
• US Class Current: 250/332
• CPC Class Codes: G01J 5/20 using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14649 Infrared imagers

Abstract

Micromachined, CMOS p⁺-active/n-well diodes are used as infrared sensing elements in uncooled Focal Plane Arrays (FPA). The FPAs are fabricated using a standard CMOS process followed by post-CMOS bulk-micromachining steps without any critical lithography or complicated deposition processes. Micromachining steps include Reactive Ion Etching (RIE) to reach the bulk silicon and anisotropic silicon wet etching together with electrochemical etch-stop technique to obtain thermally isolated p⁺-active/n-well diodes. The FPAs are monolithically integrated with their readout circuit since they are fabricated in any standard CMOS technology.

Claims

1. A single pixel microbolometer comprising:

at least one suspended diode;

an infrared absorber layer; and

at least one of support arm for holding the at least one suspended diode, wherein the at least one of the support arm for carrying electrical signals to the at least one diode using an interconnect layer.

2. The single pixel microbolometer of claim 1 wherein the diode comprises a p⁺-active/n-well diode.

3. The single pixel microbolometer of claim 1 wherein the at least one support arm comprises two support arms.

4. The single pixel microbolometer of claim 1 wherein the interconnected layer can be metal or polysilicon.

5. The single pixel microbolometer of claim 1 wherein the microbolometer is implemented by using any of a standard CMOS process, BICMOS process, SOI CMOS process and SOI BICMOS process.

6. A method for providing a single pixel microbolometer comprising:

providing connection pads protected during post-CMOS processes with polymer/metal combinations without critical post-CMOS lithography, wherein critical lithography is defined as a lithography process requiring an accuracy of less than 5 μ

m;

dry etching using CMOS metal layers as precisely defined masks for the pixel formation; and

wet-etching using a silicon etchant for creation of a suspended diode structure.

7. The method of claim 6 wherein the wet-etching comprises bulk etching of fabricated CMOS dies/wafers using an anisotropic silicon etchant;

and controlled by electrochemical etch-stop technique.

8. The method of claim 7 which includes biasing of the n-well layers of the individual diodes in a focal plane array (FPA) format with special circuitry.

9. The method of claim 6 wherein the microbolometer is implemented by using any of a standard CMOS process, BICMOS process, SOI CMOS process and SOI BICMOS process.

10. A focal plane array (FPA) comprising:

an array of single pixel microbolometers wherein each of the microbolometers comprise at least one suspended diode;

an infrared absorber layer; and

at least one of support arm for holding the at least one suspended diode, wherein the at least one of the support arm for carrying electrical signals to the at least one diode using polysilicon or metal as an interconnect layer.

11. The focal plane array of claim 10 wherein the array is sensitive to infrared radiation in the wavelength range of 6 μ

m to 18 μ

m.

12. The focal plane array of claim 10 wherein pixel cross-talk is prevented with silicon sidewalls between the pixels achieving array sizes from 8×

8 to 1024×

1024 including but not confined to non square arrays.

13. The focal plane array of claim 10 which includes:

a monolithically integrated readout circuit in standard CMOS process.

14. The focal plane array of claim 13 wherein the integrated readout circuit comprises:

row and column electronic switches allowing unique addressing of each pixel for monitoring of the diode turn on voltage in each pixel; and

a read out circuit extracting the absorbed heat information from the diode turn on voltage of each pixel.

15. The focal plane array of claim 10 wherein the microbolometer is implemented by using any of a standard CMOS process, BICMOS process, SOI CMOS process and SOI BICMOS process.

16. A method for providing a single pixel microbolometer comprising:

using the layers of CMOS process as the protection mask during post-CMOS processes;

using a post-CMS deposited polymer/metal combination as the protection of the pads and other regions that require protection during post-CMOS processes;

using Reactive Ion Etching (RIE);

etching in oxygen and flourine based gases such as CHF₃;

allowing narrow openings, resulting in high fill factor;

allowing etching of oxide layers to create openings to reach silicon; and

allowing etching of silicon to form suspended diode structures.