Nitride based semiconductor having improved external quantum efficiency and fabrication method thereof

• US 20050224816A1
• Filed: 06/23/2004
• Published: 10/13/2005
• Est. Priority Date: 03/30/2004
• Status: Abandoned Application

• Current Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: Oh, Jeong Tak, Lee, Kyu Han, Kim, Sun Woon, Kim, Je Won
• Application Number:
  US10/873,239
• Publication Number:
  US 20050224816A1
• Time in Patent Office: Days
• US Class Current: 257/79
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

A surface treated nitride semiconductor in use for a light emitting diode, in which an n-cladding layer is formed on a substrate. An active layer having a multiple quantum well structure is formed on the n-cladding layer. A p-cladding layer is formed on the active layer. A p-capping layer is formed on the p-cladding layer in a low temperature range in which single crystal growth does not take place. The p-capping layer has a nanoscale roughened structure formed in an upper surface thereof via heat treatment in a high temperature range in which at least partial crystallization takes place. The nanoscale roughened structure reduces total internal reflection of the nitride semiconductor thereby improving external quantum efficiency thereof.

Claims

1. A surface treated nitride semiconductor for a light emitting diode comprising:

an n-cladding layer formed on a substrate;

an active layer having a multiple quantum well structure formed on the n-cladding layer;

a p-cladding layer formed on the active layer; and

a p-capping layer formed on the p-cladding layer in a low temperature range in which single crystal growth does not take place, the p-capping layer having a nanoscale roughened structure formed in an upper surface thereof via heat treatment in a high temperature range in which at least partial crystallization takes place.

2. The surface treated nitride semiconductor according to claim 1, wherein the p-capping layer has an amorphous or polycrystalline structure.

3. The surface treated nitride semiconductor according to claim 1, wherein the p-capping layer is formed at a temperature range from about 300 to 700°

C.

4. The surface treated nitride semiconductor according to claim 1, wherein the p-capping layer is formed at a temperature range from about 300 to 400°

C.

5. The surface treated nitride semiconductor according to claim 1, wherein the nanoscale roughened structure has a number of protrusions having a diameter of about 5 to 500 nm.

6. The surface treated nitride semiconductor according to claim 1, wherein the nanoscale:

roughened structure has a number of pores having a width of about 5 to 500 nm.

7. The surface treated nitride semiconductor according to claim 1, wherein the nanoscale roughened structure is formed at a temperature range from about 700 to 1300°

C.

8. The surface treated nitride semiconductor according to claim 1, wherein the substrate is one selected from a group consisting of a sapphire substrate, a SiC substrate, an oxide substrate and a carbide substrate.

9. A fabrication method of surface treated nitride semiconductors for a light emitting diode, the method comprising the following steps of:

(a) forming an n-cladding layer on a substrate;

(b) forming an active layer having a multiple quantum well structure on the n-cladding layer;

(c) forming a p-cladding layer on the active layer;

(d) forming a p-capping layer on the p-cladding layer at a low temperature range in which single crystal growth does not take place; and

(e) heat treating the p-capping layer at a high temperature range, whereby the p-capping layer is at least partially crystallized to form a nanoscale roughened structure in an upper region thereof.

10. The fabrication method of surface treated nitride semiconductor according to claim 9, wherein the step (d) of forming a p-capping layer is carried out at a temperature range from about 300 to 700°

C.

11. The fabrication method of surface treated nitride semiconductor according to claim 9, wherein the step (d) of forming a p-capping layer is carried out at a temperature range from about 300 to 400°

C.

12. The fabrication method of surface treated nitride semiconductor according to claim 9, wherein the step (d) of forming a p-capping layer is carried out at a predetermined molar ratio of III group element to V group element in the range from about 10 to 5000.

13. The fabrication method of surface treated nitride semiconductor according to claim 9, wherein the step (d) of forming a p-capping layer is carried out at a predetermined molar ratio of III group element to V group element in the range from about 10 to 1000.

14. The fabrication method of surface treated nitride semiconductor according to claim 9, wherein the heat treatment step (e) is carried out in a temperature range from about 700 to 1300°

C.

15. The fabrication method of surface treated nitride semiconductor according to claim 14, wherein the heat treatment step (e) is carried out for about 1 to 10 minutes.

16. The fabrication method of surface treated nitride semiconductor according to claim 14, wherein the heat treatment step (e) is carried out for about 2 to 7 minutes.

17. The fabrication method of surface treated nitride semiconductor according to claim 9, wherein the heat treatment step (e) comprises feeding anti-decomposition gas at a flow rate in the range from about 2 to 10 liters per minute for preventing decomposition of the p-capping layer, wherein the anti-decomposition gas is at least one selected from a group consisting of ammonia (NH₃), tertiarybutylamine (N(C₄H₉)H₂), phenylhydrazine (C₆H₈N₂) and dimethylhydrazine (C₂H₈N₂).

18. The fabrication method of surface treated nitride semiconductor according to claim 17, wherein nitrgen or inactive gas is fed together with the anti-decomposition gas.

19. The fabrication method of surface treated nitride semiconductor according to claim 9, wherein the substrate is one selected from a group consisting of a sapphire substrate, a SiC substrate, an oxide substrate and a carbide substrate.