Solid-state image pickup device

• US 20050224841A1
• Filed: 04/04/2003
• Published: 10/13/2005
• Est. Priority Date: 04/04/2002
• Status: Active Grant

• Current Assignee: Sony Semiconductor Solutions Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Sato, Hiroki, Nakamura, Nobuo, Fujita, Hiroaki, Mabuchi, Keiji, Abe, Takashi, Funatsu, Eiichi, Umeda, Tomoyuki
• Granted Patent: US 7,515,185 B2
• Time in Patent Office: Days
• US Class Current: 257/215
• CPC Class Codes: H04N 25/626 Reduction of noise due to residual charges remaining after image readout, e.g. to remove ghost images or afterimages
• CPC Class Codes: H04N 25/709 Circuitry for control of the power supply
• CPC Class Codes: H04N 25/766 comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power

Abstract

A solid-state imaging device for enlarging an operating margin of a pixel portion and achieving complete transfer of a signal charge by using a plurality of power supply voltages, wherein a plurality of power supplies having different power supply voltage values are supplied to portions of a semiconductor chip 1. For example, as a first power supply system, a first digital power supply voltage (DVDD1) is supplied from a power supply terminal 45, a first digital ground voltage (DVSS1) is supplied from a power supply terminal 46, a second digital power supply voltage (DVDD2) is supplied from a power supply terminal 47, a second digital ground voltage (DVSS2) is supplied from a power supply terminal 48, a third digital power supply (DVDD3) is supplied from a power supply terminal 49, and a third digital ground voltage (DVSS3) is supplied from a power supply terminal 50, and as a second power supply system, a first analog power supply voltage (AVDD1) is supplied from a power supply terminal 40, a first analog ground voltage (AVSS1) is supplied from a power supply terminal 41, a second analog power supply voltage (AVDD2) is supplied from a power supply terminal 42, and a second analog ground voltage (AVSS2) is supplied from a power supply terminal 43.

Claims

1. A solid-state imaging device having a pixel portion comprised of a plurality of unit pixels and a peripheral circuit portion for controlling the pixel portion, wherein the peripheral circuit operates supplied with a first power supply voltage of a first power supply system and the pixel portion operates supplied with a second power supply voltage having a value different from that of the first power supply voltage of the second power supply system,

said solid-state imaging device characterized by comprising:

a first power supply inputting means for receiving as input the first power supply voltage of the first power supply system from the outside and

a second power supply inputting means for receiving as input the second power supply voltage of the second power supply system from the outside and supplying the same to the pixel portion.

2. A solid-state imaging device as set forth in claim 1, characterized by further comprising a column area for storing signals of each pixel row adjoining said pixel portion.

3. A solid-state imaging device as set forth in claim 2, characterized by further comprising a level shifting means for converting a level of said first power supply voltage and by supplying a power supply voltage generated by said level shifting means to a predetermined location.

4. A solid-state imaging device as set forth in claim 2, characterized in that at least one of said first and second power supply voltages is a negative power supply voltage.

5. A solid-state imaging device as set forth in claim 3, characterized in that:

said unit pixel has at least a photo-electric conversion unit generating a signal charge in accordance with an amount of light received, a charge detection unit for acquiring a signal charge genereated by said photo-electric conversion unit, a transferring means for transferring a signal charge generated by said photo-electric conversion unit to said charge detection unit, a resetting means for resetting said photo-electric conversion unit, and an amplifying means for converting a signal charge of said charge detection unit to an electric signal and outputting it to an output signal line, and

said level shifting means supplies a level shifted power supply voltage to the transferring means and resetting means.

6. A solid-state imaging device as set forth in claim 5, characterized in that said level shifting means supplies a power supply voltage value for supplying to the transferring means set higher than the power supply voltage value for supplying to said resetting means.

7. A solid-state imaging device as set forth in claim 3, characterized by having at least a circuit area operating by a first power supply voltage value and a circuit area operating by a second power supply voltage value and inserting said level shifting means in an area connecting circuit areas differing in power supply voltage value to convert the power supply voltage values.

8. A solid-state imaging device as set forth in claim 1, characterized by further comprising a vertical drive portion for driving said pixel portion, a source of a reset transistor forming said resetting means connected to said charge detection unit, and a drain of said reset transistor controlled by said vertical drive portion.

9. A solid-state imaging device as set forth in claim 8, characterized in that said drain control line is supplied with a third power supply voltage during a period other than the read period of the signal charge and is supplied with a fourth power supply voltage higher than said third power supply voltage during the read period of the signal charge, the fourth power supply voltage is used for reset of said charge detection unit and a series of read operations including reading of the signal charge, and the applied voltage of said drain control line is returned to said third power supply voltage after the end of the read operation of said signal charge.

10. A solid-state imaging device as set forth in claim 8, characterized in that a thickness of a gate insulation film of each transistor of said pixel portion is larger than a thickness of a gate insulation film of transistors at the peripheral circuit portion other than said pixel portion.

11. A solid-state imaging device as set forth in claim 8, characterized by further comprising a control transistor for controlling a gate of said reset transistor to a floating state, holding a gate of said reset transistor at a second state to set it at a first voltage when said drain control line is a first state, then setting said drain control line to a second state to set the gate of the reset transistor to a second voltage larger than the first voltage by capacitance coupling.

12. A solid-state imaging device as set forth in claim 11, characterized in that said unit pixel further comprises a selection transistor for selecting a pixel row, sets said reset transistor to the ON state to set said charge detection unit to the first voltage, sets said reset transistor to the OFF state to set said charge detection unit to a floating state, then sets said selection transistor to the ON state so as to boost said charge detection unit to the second voltage by the parasitic capacitance of the source of said selection transistor and said charge detection unit.

13. A solid-state imaging device as set forth in claim 11, characterized in that said unit pixel further comprises a selection transistor for selecting a pixel row, each said unit pixel has at least one power supply voltage source, a connection order in each unit pixel is the power supply voltage source, selection transistor, amplification transistor, and output signal line, and the order of driving said pixel portion is first to turn said reset transistor ON once, then turn said selection transistor ON so as to read out a signal charge of said photo-electric conversion unit.

14. A solid-state imaging device as set forth in claim 4, characterized in that

a pixel portion forming area on the semiconductor substrate is formed with a first well area of a first conductivity type, the outer circumference is formed with a second well area of a second conductivity type, and the further outer circumference is formed with a third well area of the first conductivity type, and

said third well area is supplied with a negative power supply voltage, the inside of said third well area is formed with an n-channel insulating gate type field effect transistor, and a source of said n-channel insulating gate type field effect transistor and said third well area are made the same negative power supply voltage.

15. A solid-state imaging device having a pixel portion comprised of a plurality of unit pixels and a peripheral circuit portion for controlling the pixel portion, wherein the peripheral circuit operates supplied with a first power supply voltage and the pixel portion operates supplied with a second power supply voltage having a value different from that of the first power supply voltage,

side solid-state imaging device characterized by comprising:

a power supply inputting means for receiving as input a power supply voltage of a single level from the outside and

a level shifting means for converting the level of the power supply voltage received as input by the power supply inputting means to the first power supply voltage and/or second power supply voltage, wherein

the first power supply voltage generated by the level shifting means is selectively supplied to the peripheral circuit portion, and the generated second power supply voltage is selectively supplied to the pixel portion.

16. A solid-state imaging device as set forth in claim 15, characterized by further comprising a column area for storing signals of each pixel row adjoining said pixel portion.

17. A solid-state imaging device as set forth in claim 15, characterized in that at least one of said plurality of power supply voltages is a negative power supply voltage.

18. A solid-state imaging device as set forth in claim 15, characterized in that:

said unit pixel has at least a photo-electric conversion unit generating a signal charge in accordance with an amount of light received, a charge detection unit for acquiring a signal charge genereated by said photo-electric conversion unit, a transferring means for transferring a signal charge generated by said photo-electric conversion unit to said charge detection unit, a resetting means for resetting said photo-electric conversion unit, and an amplifying means for converting a signal charge of said charge detection unit to an electric signal and outputting it to an output signal line, and

said level shifting means supplies a level shifted power supply voltage to the transferring means and resetting means.

19. A solid-state imaging device as set forth in claim 18, characterized in that said level shifting means supplies a power supply voltage value for supplying to the transferring means set higher than the power supply voltage value for supplying to said resetting means.

20. A solid-state imaging device as set forth in claim 15, characterized by having at least a circuit area operating by a first power supply voltage value and a circuit area operating by a second power supply voltage value and inserting said level shifting means in an area connecting circuit areas differing in power supply voltage value to convert the power supply voltage values.

21. A solid-state imaging device as set forth in claim 15, characterized by further comprising a vertical drive portion for driving said pixel portion, a source of a reset transistor forming said resetting means connected to said charge detection unit, and a drain of said reset transistor controlled by said vertical drive portion.

22. A solid-state imaging device as set forth in claim 21, characterized in that said drain control line is supplied with a third power supply voltage during a period other than the read period of the signal charge and is supplied with a fourth power supply voltage higher than said third power supply voltage during the read period of the signal charge, the fourth power supply voltage is used for reset of said charge detection unit and a series of read operations including reading of the signal charge, and the applied voltage of said drain control line is returned to said third power supply voltage after the end of the read operation of said signal charge.

23. A solid-state imaging device as set forth in claim 21, characterized in that a thickness of a gate insulation film of each transistor of said pixel portion is larger than a thickness of a gate insulation film of transistors at the peripheral circuit portion other than said pixel portion.

24. A solid-state imaging device as set forth in claim 21, characterized by further comprising a control transistor for controlling a gate of said reset transistor to a floating state, holding a gate of said reset transistor at a second state to set it at a first voltage when said drain control line is a first state, then setting said drain control line to a second state to set the gate of the reset transistor to a second voltage larger than the first voltage by capacitance coupling.

25. A solid-state imaging device as set forth in claim 24, characterized in that said unit pixel further comprises a selection transistor for selecting a pixel row, sets said reset transistor to the ON state to set said charge detection unit to the first voltage, sets said reset transistor to the OFF state to set said charge detection unit to a floating state, then sets said selection transistor to the ON state so as to boost said charge detection unit to the second voltage by the parasitic capacitance of the source of said selection transistor and said charge detection unit.

26. A solid-state imaging device as set forth in claim 24, characterized in that said unit pixel further comprises a selection transistor for selecting a pixel row, each said unit pixel has at least one power supply voltage source, a connection order in each unit pixel is the power supply voltage source, selection transistor, amplification transistor, and output signal line, and the order of driving said pixel portion is first to turn said reset transistor ON once, then turn said selection transistor ON so as to read out a signal charge of said photo-electric conversion unit.

27. A solid-state imaging device as set forth in claim 17, characterized in that

a pixel portion forming area on the semiconductor substrate is formed with a first well area of a first conductivity type, the outer circumference is formed with a second well area of a second conductivity type, and the further outer circumference is formed with a third well area of the first conductivity type, and

said third well area is supplied with a negative power supply voltage, the inside of said third well area is formed with an n-channel insulating gate type field effect transistor, and a source of said n-channel insulating gate type field effect transistor and said third well area are made the same negative power supply voltage.