Semiconductor device, manufacturing process thereof and imaging device

• US 20050224853A1
• Filed: 03/31/2005
• Published: 10/13/2005
• Est. Priority Date: 03/19/2003
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Ohkawa, Narumi
• Granted Patent: US 7,619,269 B2
• Time in Patent Office: Days
• US Class Current: 257/296
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

A semiconductor device including a pixel region in which one or more pixels are formed and a DRAM cell region in which one or more DRAM cells for storing output signals from the pixels are formed, characterized in that the layers constituting the pixel region and the DRAM cell region are formed in the same semiconductor process.

Claims

1. A semiconductor device, comprising:

a pixel region in which one or more pixels are formed; and

a storage element region in which one or more storage elements for storing output signals from said pixels are formed, wherein

each of the layers constituting said pixel region and said storage element region is formed in the same process.

2. The semiconductor device according to claim 1, wherein said storage element has a roughened surface configuration.

3. The semiconductor device according to claim 2, wherein said storage element is a stack type capacitor.

4. The semiconductor device according to claim 1, wherein said storage element is a trench type capacitor.

5. The semiconductor device according to claim 1, wherein said storage element is a flash memory cell.

6. The semiconductor device according to claim 1, wherein a bit line connected to said storage element and a part of wiring structure connected to said pixel are formed in the same process.

7. The semiconductor device according to claim 6, wherein said pixel includes an imaging element and a storage section for temporarily holding a charge generated by said imaging element,

said wiring structure connected to said storage section is formed along with the bit line in the same process.

8. The semiconductor device according to claim 7, wherein said pixel further includes a transfer transistor for switching the transfer operation of the charge from said imaging element to said storage section,

said wiring structure connected to the gate electrode of said transfer transistor is formed along with said bit line in the same process.

9. The semiconductor device according to claim 1, further comprising a fuse for pixel for adjusting the voltage supplied to said pixel.

10. The semiconductor device according to claim 9, further comprising a fuse for storage element for adjusting the voltage supplied to said storage element, wherein

said fuse for pixel and said fuse for storage element are formed in the same process.

11. The semiconductor device according to claim 1, further comprising an internal voltage generation circuit for generating a voltage to be supplied to each of said pixel and said storage element.

12. The semiconductor device according to claim 11, wherein

said pixel includes at least a reset transistor for resetting electrical charge held by said storage section,

said internal voltage generation circuit supplies a minus voltage to said reset transistor as a gate voltage when said reset transistor is turned off.

13. The semiconductor device according to claim 12, wherein said internal voltage generation circuit supplies a word line negative reset voltage for said storage element to said reset transistor as a gate voltage when said reset transistor is turned off.

14. The semiconductor device according to claim 1, wherein a part of all output signals from said plurality of pixels stored in said storage element is outputted to the outside of the semiconductor device, and after that if any instruction is given, said all output signals are outputted from said storage element to the outside of the semiconductor device.

15. The semiconductor device according to claim 1, further comprising signal read out unit for reading out the output signals from said plurality of pixels disposed in a matrix configuration, wherein

said signal read out unit includes a first signal read out section for pixels disposed in odd lines and a second signal read out section for pixels disposed in even lines.

16. The semiconductor device according to claim 15, wherein said first signal read out section and said second signal read out section include a number of signal read out circuits corresponding to the kinds of color signals obtained by said each pixel respectively.

17. An imaging device, comprising:

an imaging element and one or more pixels including a reset transistor of which one impurity diffusion layer functions as a storage section for temporarily holding a charge generated by said imaging element, wherein

a voltage lower than a value in which a voltage impressed to the gate electrode of said reset transistor is subtracted by a threshold voltage of said reset transistor is once impressed to the other impurity diffusion layer of said reset transistor, after that, by impressing a voltage, which is substantially the same level as that of the impressed voltage to said gate electrode, to said other impurity diffusion layer, the electrical charge held by said storage section is reset.

18. The imaging device according to claim 17, wherein said signal read out unit reads out output signals from said plurality of pixels in a manner of CDS (correlated double sampling).

19. The imaging device according to claim 18, further comprising:

an internal voltage generation circuit that generates a voltage to be supplied to said pixels,

a row select circuit that selects the objective pixels of which signals are read out by said signal read out unit in said plurality of pixels disposed in a matrix configuration on the basis of row, and is capable of controlling the voltage value supplied to said pixels from said internal voltage generation circuit, wherein

said pixels further include a transfer transistor for switching the transfer operation of the charge from said imaging element to said storage section,

the signal line connected to the gate electrode of said transfer transistor is connected to said internal voltage generation circuit and disposed in the line direction of said pixel group,

the signal line connected to the gate electrode of said reset transistor is connected to said row select circuit and disposed in the row direction of said pixel group.

20. A manufacturing method of a semiconductor device including a pixel region in which one or more pixels are formed and a storage element region in which one or more storage elements for storing output signals from said pixels are formed, comprising the step of:

forming each of layers constituting said pixel region and said storage element region in the same process.

21. The manufacturing method of a semiconductor device according to claim 20, wherein the surface of said storage element is roughened.

22. The manufacturing method of a semiconductor device according to claim 20, wherein a bit line connected to said storage element and a part of wiring structure connected to said pixel are formed in the same process.

23. The manufacturing method of a semiconductor device according to claim 22, wherein said pixel includes an imaging element and a storage section for temporarily holding a charge generated by said imaging element,

a wiring structure connected to said storage section is formed along with said bit line in the same process.

24. The manufacturing method of a semiconductor device according to claim 23, wherein said pixel further includes a transfer transistor for switching the transfer operation of the charge from said imaging element to said storage section,

a wiring structure connected to the gate electrode of said transfer transistor is formed along with said bit line in the same process.

25. The manufacturing method of a semiconductor device according to claim 20, wherein a fuse for pixel for adjusting the voltage to be supplied to said pixel is formed.

26. The manufacturing method of a semiconductor device according to claim 25, wherein a fuse for storage element for adjusting the voltage to be supplied to said storage element and said fuse for pixel are formed in the same process.

27. A semiconductor device, comprising:

a pixel region in which one or more pixels are formed,

a fuse for the pixel region,

a color filter and micro-lens on the pixel region.

28. The semiconductor device according to claim 27,

wherein said color filter and micro-lens are not on the fuse.