MOS-gated device having a buried gate and process for forming same

• US 20050224868A1
• Filed: 03/28/2005
• Published: 10/13/2005
• Est. Priority Date: 03/01/1999
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Zeng, Jun, Kocon, Christopher B.
• Granted Patent: US 7,388,254 B2
• Time in Patent Office: Days
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions. A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer. A process for forming an improved MOS-gate device provides a device whose gate trench is filled to a selected level with a conductive gate material, over which is formed an isolation dielectric layer whose upper surface is substantially coplanar with the upper surface of the upper layer of the device.

Claims

1. An improved trench MOS-gated device comprising:

a substrate with a surface source region;

a trench through the source region to define vertical surfaces in the source adjacent the trench;

a drain disposed beneath the trench;

said trench at least partially lined with insulating material, it lower portion partially filled with conductive material, and its upper portion partially filled with insulating material to leave at least a portion of the vertical surfaces of the source adjacent the surface of the substrate without insulation;

a metal contact layer on the substrate surface of the source and on the vertical surface of the source adjacent the surface.

2. The device of claim 1 wherein:

the source region is of a first polarity and highly doped;

the substrate further comprises a drain structure with a lightly doped layer of the first polarity over a heavily doped layer of the first polarity, and

a body region over the lightly doped drain region.

3. The device of claim 2 further comprising a well region over the drain structure and comprising a lightly doped region of a second, opposite polarity.

4. The device of claim 2 further wherein the substrate comprises heavily doped body tie regions of said second polarity adjacent the source regions in the surface of the substrate.

5. The device of claim 1 wherein said gate trench has a floor and sidewalls, a first insulating layer covers the floor and extends up the sidewalls to a location at least proximate the depth of the source regions, and a conductive gate material partially fills the trench and extends from the insulated floor to a height proximate the depth of the source regions.

6. The device of claim 3 wherein the trench further comprises an insulating layer covering the conductive gate material and extending toward the surface of the trench and terminating at a location below the surface of the trench to leave a portion of the source adjacent the trench without insulation.

7. The device of claim 1 further comprising an array with a plurality of body regions, a plurality of source regions, and a plurality of trenches to comprise alternating body regions and source regions each disposed adjacent to a gate trench, and wherein one of said arrays is separated from a second of said arrays by said gate trench.

8. The device of claim 7 wherein said array of alternating body regions and source regions has a lengthwise dimension along said gate trench, said source regions comprising a greater portion and said body regions comprising a lesser portion of said lengthwise dimension.

9. The device of claim 1 wherein the selected level of gate material in the trench is substantially coplanar with the selected depth of the source regions in the upper layer.

10. The device of claim 1 wherein said dielectric material forming said sidewalls, said floor, and said isolation layer in said gate trench comprises silicon dioxide.

11. The device of claim 1 wherein said conductive gate material within said gate trench is selected from the group consisting of a metal, a silicide, and doped polysilicon.

12. The device of claim 1 wherein said first polarization is P and said second polarization is N.

13. The device of claim 1 wherein said first polarization is N and said second polarization is P.

14. The device of claim 1 comprising a plurality of gate trenches having an open-cell stripe topology.

15. The device of claim 1 comprising a plurality of gate trenches having a closed-cell cellular topology.

17. The device of claim 1 wherein said device is a power MOSFET.

18. The device of claim 1 wherein said device is an insulated gate bipolar transistor.

19. The device of claim 1 wherein the device is a MOS-controlled thyristor.

16. The device of claim 16 wherein cells in said closed-cell cellular topology have a square configuration or a hexagonal configuration.