Power semiconductor device with buried source electrode

• US 20050224871A1
• Filed: 04/04/2005
• Published: 10/13/2005
• Est. Priority Date: 04/09/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Ma, Ling
• Granted Patent: US 8,564,051 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power semiconductor device that includes a buried source electrode disposed at the bottom of a trench below a respective gate electrode, and a source connector including a finger electrically connecting the buried source to the source contact of the device, and a process for fabricating the device.

Claims

1. A power semiconductor device comprising:

a base region;

a common conduction region below said base region;

a plurality of trenches extending through said base region, each trench including a bottom and opposing sidewalls;

a gate electrode disposed inside each trench and insulated from said base region by a respective gate insulation layer;

a buried source electrode in each trench disposed below and insulated from a respective gate electrode;

a source electrode connector including fingers each disposed within a respective trench and electrically connected to a respective buried source electrode; and

a source electrode in electrical contact with said fingers.

2. A power semiconductor device according to claim 1, wherein each finger is adjacent to and insulated from a respective gate electrode.

3. A power semiconductor device according to claim 1, wherein said source electrode connector includes a strip extending across said trenches and electrically connected to said fingers.

4. A power semiconductor device according to claim 1, wherein said source electrode connector is comprised of polysilicon.

5. A power semiconductor device according to claim 1, wherein each buried source electrode is insulated from said common conduction region by an insulation body.

6. A power semiconductor device according to claim 5, wherein said insulation body is thicker than said gate insulation layer.

7. A power semiconductor device according to claim 1, wherein said gate insulation layer is comprised of silicon dioxide.

8. A power semiconductor device according to claim 5, wherein said insulation body is comprised of silicon dioxide.

9. A power semiconductor device according to claim 1, wherein said common conduction region and said base region are formed in a silicon body, said silicon body being disposed over a silicon substrate.

10. A power semiconductor device according to claim 10, further comprising a drain contact electrically connected to said substrate.

11. A process for fabricating a power semiconductor device comprising:

forming a plurality of trenches in a trench receiving semiconductor body;

forming an oxidation retardant layer on sidewalls of said trenches;

removing a portion of the bottom of each of said trenches to form recesses at the bottom of each of said trenches, each recess including a bottom portion and opposing sidewalls;

oxidizing said bottom portion and said sidewalls of said recesses to form an insulation body;

forming a buried source electrode in each said recess adjacent said insulation body; and

forming an insulated gate structure above each said buried source electrode.

12. A process according to claim 11, wherein said semiconductor body includes a common conduction region of one conductivity and a base region of a second conductivity, said trenches extending to a depth below said base region and terminating in said common conduction region.

13. A process according to claim 11, further comprising forming a source electrode connector, said source electrode connector including fingers each disposed within a respective trench and electrically connected to a respective buried source electrode.

14. A process according to claim 13, wherein said source electrode connector includes a strip extending across said trenches and electrically connected to said fingers.

15. A process according to claim 13, wherein said source electrode connector is comprised of polysilicon.

16. A process according to claim 13, wherein said buried source electrodes and said source electrode connector are formed by depositing polysilicon in said trenches, and removing a portion of said deposited silicon to define said buried source electrodes and said fingers.

17. A process according to claim 16, further comprising oxidizing the exposed surfaces of said fingers and said buried source electrodes prior to forming said insulated gate structures.

18. A process according to claim 17, further comprising oxidizing said oxidation retardant layer from said sidewalls of said trenches, oxidizing said sidewalls to form gate insulation on said sidewalls, and then forming gate electrodes in said trenches adjacent said gate insulation on said sidewalls to form a gate structure above each buried source electrode.