Semiconductor device for power MOS transistor module

• US 20050224887A1
• Filed: 06/28/2004
• Published: 10/13/2005
• Est. Priority Date: 04/09/2004
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsuki, Hirobumi, Hiyama, Yuji, Oota, Tsuyoshi
• Granted Patent: US 6,992,351 B2
• Time in Patent Office: Days
• US Class Current: 257/368
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A first transistor has a first main electrode region which is formed so that these are subdivided into a plurality of first isolated island region. A second transistor has its first main electrode region which are divided into a plurality of second isolated island regions in close proximity to the array of first island regions.

Claims

1. A semiconductor device comprising:

a semiconductor substrate; and

a first transistor and a second transistor formed on said semiconductor substrate, each of the first and second transistors having a first main electrode region formed on one surface side of said substrate, a second main electrode region formed on the other surface side of said substrate, and a gate electrode for control of a current flowable between said first main electrode region and said second main electrode region, while letting said second main electrode region be owned in common by said first and second transistors, wherein

said first main electrode region of said first transistor is formed to be divided into a plurality of first isolated island regions on the one surface side of said semiconductor substrate,

said first main electrode region of said second transistor is formed on the one surface side of said semiconductor substrate and is divided into a plurality of second isolated island regions as laid out adjacent to at least part of said plurality of first isolated island regions,

at a portion whereat neighboring ones of said first isolated island regions face each other, the neighboring first isolated island regions are combined together into a unified first isolated island region, and in this unified first isolated island region said first main electrode region of said first transistor is integrally formed,

at a portion whereat neighboring ones of said second isolated island regions face each other, the neighboring second isolated island regions are combined together into a unified second isolated island region, and in this united second isolated island region said second main electrode region is integrally formed,

said first isolated island regions and said second isolated island regions are organized into at least first groups being alternately placed while letting a contour extending in a first direction be an adjacent portion and second groups being alternately placed while letting a contour extending in a second direction other than said first direction be an adjacent portion,

one of the first isolated island regions of said first groups and its neighboring one of the first isolated island regions of said second groups are combined together into said unified first isolated island region, and

one of the second isolated island regions of said first groups and its neighboring one of the second isolated island regions of said second groups are combined together into said unified second isolated island region.

2. The semiconductor device according to claim 1, wherein said gate electrode of said first transistor has a first connection region for connection to an external wiring line,

said gate electrode of said second transistor has a second connection region for connection to an external wiring line, and

the second isolated island regions of said second groups have an array of portions as laid out in said first direction together with said first connection region and said second connection region.

3. The semiconductor device according to claim 2, wherein the second isolated island region of said second groups is placed between said first connection region and said second connection region.

4. The semiconductor device according to claim 1, wherein a boundary line between said first isolated island regions and said second isolated island regions is a straight line in shape.

5. The semiconductor device according to claim 1, wherein a boundary line between said first isolated island regions and said second isolated island regions has a shape like a curved line with an alternate layout of protuberances and depressions.

6. The semiconductor device according to claim 1, wherein a boundary line between said first isolated island regions and said second isolated island regions is a wavy line in shape.

7. A semiconductor device comprising:

a semiconductor substrate; and

a first transistor and a second transistor formed above said semiconductor substrate, each of the first and second transistors having a first main electrode region formed on one surface side of said substrate, a second main electrode region formed on the other surface side of said substrate, and a gate electrode formed on the one surface side of said substrate for controlling a current flowable between said first main electrode region and said second main electrode region, while letting said second main electrode region be owned in common by said first and second transistors, wherein

said first main electrode region of said first transistor is formed to be divided into a plurality of first isolated island regions on the one surface side of said semiconductor substrate, said first isolated island regions being commonly connected together to a first electrode wiring line through a plurality of first electrode layers formed at respective upper surfaces of said first isolated island regions,

said first main electrode region of said second transistor is formed on the one surface side of said semiconductor substrate and is divided into a plurality of second isolated island regions in close proximity to said plurality of first isolated island regions, said plurality of second isolated island regions being commonly connected together to a second electrode wiring line via a plurality of second electrode layers formed at respective upper surfaces of said second isolated island regions,

said gate electrode of said first transistor has a first connection region as connected to a first external gate wiring line,

said gate electrode of said second transistor has a second connection region being laid out in a first direction together with said first connection region and being connected to a second external gate wiring line,

said plurality of first isolated island regions and said plurality of second isolated island regions are arrayed in a second direction crossing said first direction,

said plurality of first isolated island regions including a specified first isolated island region neighboring upon said first connection region and having a first portion aligned in said first direction together with said first connection region, and

said plurality of second isolated island regions including a specified second isolated island region neighboring upon said second connection region and having a second portion aligned in said first direction together with said second connection region.

8. The semiconductor device according to claim 7, wherein said specified first isolated island region has a third portion extending in the first direction together with a remaining portion of said specified second isolated island region other than said second portion thereof.

9. The semiconductor device according to claim 8, wherein said first portion and said second portion are placed between said first connection region and said second connection region.

10. The semiconductor device according to claim 8, wherein said first electrode wiring line and said second electrode wiring line are plate-like electrodes.

11. The semiconductor device according to claim 8, wherein said first electrode wiring line and said second electrode wiring line are plate-like electrodes with their elongate direction identical to a direction along which said plurality of first main electrodes and said plurality of second main electrodes are queued.

12. The semiconductor device according to claim 11, wherein said first external gate wiring line and said second external gate wiring line are plate-like electrodes.

13. The semiconductor device according to claim 11, wherein said first external gate wiring line and said second external gate wiring line are plate-like electrodes with their elongate direction identical to a direction along which said plurality of first main electrodes and said plurality of second main electrodes are lined up.

14. The semiconductor device according to claim 13, wherein said first external gate wiring line and said second external gate wiring line are extended in an opposite direction to said first electrode wiring line and said second electrode wiring line.

15. The semiconductor device according to claim 7, wherein a boundary line between said first isolated island regions and said second isolated island regions is a straight line in shape.

16. The semiconductor device according to claim 7, wherein a boundary line between said first isolated island regions and said second isolated island regions has a shape like a curved line with an alternate layout of protuberances and depressions.

17. The semiconductor device according to claim 7, wherein a boundary line between said first isolated island regions and said second isolated island regions is a wavy line in shape.

18. The semiconductor device according to claim 7, wherein said plurality of first electrode layers and said plurality of second electrode layers are alternately placed in the second direction.

19. The semiconductor device according to claim 7, wherein said first electrode layers are connected through bumps to said first electrode wiring line whereas said second electrode layers are connected via bumps to said second electrode wiring line.

20. The semiconductor device according to claim 7, wherein said first electrode layers are connected by bonding to said first electrode wiring line whereas said second electrode layers are connected by bonding to said second electrode wiring line.