Self aligned contact in a semiconductor device and method of fabricating the same
First Claim
1. A method of fabricating a self aligned contact in a semiconductor device comprising:
- etching a trench in a core area and partially extending into a termination area of a substrate;
growing a first oxide on said substrate proximate a wall and a bottom of said trench;
depositing a polysilicon layer in said core area and said termination area; and
selectively etching said polysilicon layer to form a gate region in said core area portion of said trench wherein a first portion of a gate interconnect region is formed in said termination area portion of said trench and a second portion of said gate interconnect region is formed in said termination area outside of said trench.
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Accused Products
Abstract
A method of fabricating a self-aligned contact in a semiconductor device, in accordance with one embodiment of the present invention, includes etching a trench in a core area and partially extending into a termination area of a substrate. A first oxide is grown on the substrate proximate the trench. A polysilicon layer is deposited in the core area and the termination area. The polysilicon layer is selectively etched to form a gate region in the core area portion of the trench. The etching of the polysilicon layer also forms a first portion of a gate interconnect region in the termination area portion of the trench and a second portion in the termination area outside of the trench.
61 Citations
20 Claims
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1. A method of fabricating a self aligned contact in a semiconductor device comprising:
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etching a trench in a core area and partially extending into a termination area of a substrate;
growing a first oxide on said substrate proximate a wall and a bottom of said trench;
depositing a polysilicon layer in said core area and said termination area; and
selectively etching said polysilicon layer to form a gate region in said core area portion of said trench wherein a first portion of a gate interconnect region is formed in said termination area portion of said trench and a second portion of said gate interconnect region is formed in said termination area outside of said trench. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of fabricating a trench metal-oxide-semiconductor field effect transistor comprising:
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depositing a sacrificial oxide layer on a substrate;
depositing a first nitride layer on said sacrificial oxide layer;
etching a trench through said first nitride layer and said sacrificial oxide layer and into a core area and partially extending into a termination area of said substrate;
growing a first portion of a gate insulator region on said substrate proximate a walls and bottom of said trench to form a first portion of a gate insulator region;
depositing a polysilicon layer in said core area and said termination area;
etching-back said polysilicon to form a gate region in said core area portion of said trench and to form a gate interconnect region in said termination area;
depositing a dielectric layer on said gate region, gate interconnect region and said first nitride layer;
etching-back said dielectric layer to form a second portion of said gate insulator region about said gate region and said gate interconnect region;
removing said first nitride layer in said core area;
implanting a body region in an upper portion of said substrate proximate said gate region to form a drain region in a lower portion of said substrate; and
implanting a source region in said body region proximate said gate region, wherein said source region is separated from said drain region by said body region. - View Dependent Claims (9, 10, 11, 12, 13)
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14. A trench metal-oxide-semiconductor field effect transistor comprising:
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a substrate having a core area and a termination area;
a drain region formed in said substrate;
a trench formed in said core area and extending into a portion of said termination area;
a polysilicon layer formed in said trench and extending into said termination area, wherein a first portion of said polysilicon layer in said core area forms a gate region and a second portion of said polysilicon layer in said termination area forms a gate interconnect region;
a gate insulator region formed about said polysilicon layer;
a body region formed in said substrate proximate said trench and above said drain region; and
a source region formed in said body region proximate said trench and separated from said drain region by said body region. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification