LED buck regulator control IC

• US 20050225259A1
• Filed: 04/05/2005
• Published: 10/13/2005
• Est. Priority Date: 04/08/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Green, Peter
• Granted Patent: US 7,301,288 B2
• Time in Patent Office: Days
• US Class Current: 315/224
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H05B 45/375 using buck topology
• CPC Class Codes: H05B 45/39 Circuits containing inverter bridges
• CPC Class Codes: Y02B 20/30 Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A high speed buck control IC for constant LED current regulation. A continuous mode hysteretically controlled buck regulator monitors the load current using an accurate on-chip band-gap voltage reference. This style of current regulation allows the designer to dispense with large and sometimes bulky output capacitors. The IC is inherently protected against short circuit conditions, and an additional circuit provides open circuit protection. An external high side bootstrap circuit aids in driving the buck switching element especially at high frequencies. A low side driver is also provided for use, e.g. in synchronous rectifier designs. All functions are realized within a small 8 pin DIP or SOIC package.

Claims

1. A buck power supply circuit for providing regulated current to a load, comprising:

first and second switching devices connected in series in a half-bridge arrangement;

first and second drivers for said first and second switching devices, respectively;

an inductor connected at one end to a connection point between said first and second switching devices and at the other end providing an output voltage to said load;

a feedback circuit connected to said load for providing a feedback voltage representative of output current in said load;

a comparator connected to both of said first and second drivers through a logic network, providing hysteretic control of said drivers such that said output voltage to said load and thereby said load current is maintained between upper and lower limits;

said feedback voltage being fed back to said comparator for establishing said upper limit of said output voltage;

a reference voltage circuit connected to said comparator for establishing said lower limit of said output voltage.

2. The circuit of claim 1, wherein said load comprises at least one LED.

3. The circuit of claim 1, wherein said reference voltage circuit is a bandgap voltage reference circuit.

4. The circuit of claim 1, further comprising an enable circuit connected to one of said comparators for receiving an enable signal, said enable circuit being operable for setting said output voltage at a selected value.

5. The circuit of claim 4, wherein said enable circuit is responsive to said enable signal for regulating the duty cycle of said output voltage.

6. The circuit of claim 5, wherein said load comprises at least one LED, and said enable circuit is operable for dimming said at least one LED.

7. The circuit of claim 5, wherein said load comprises at least one LED, and said enable circuit is operable for high-speed switching of said at least one LED to produce an animation effect.

8. The circuit of claim 4, wherein said enable circuit is responsive to said enable signal for clamping said output voltage at a selected value.

9. The circuit of claim 4, further comprising an open circuit detecting circuit which receives said output voltage and, when said output voltage exceeds a predetermined value, supplies a clamping signal to said enable circuit.

10. The circuit of claim 9, wherein said open circuit detecting circuit comprises a voltage divider, and a Zener diode connected to said enable circuit, wherein said Zener diode conducts in response to a selected output voltage of said voltage divider, thereby supplying said clamping signal.

11. The circuit of claim 1, further comprising a watchdog timer circuit responsive to said output voltage which, when said output voltage exceeds a predetermined value for a first predetermined time, issues signals to said first and second drivers for a second predetermined time.

12. The circuit of claim 1, wherein said first and second drivers, comparator, logic network and reference voltage circuit are provided on a single semiconductor chip.

13. The circuit of claim 12, wherein said enable circuit is connected to a single pin of said chip, thereby providing one-pin control of both output duty cycle and output clamping.

14. A method of providing regulated current to a load, comprising the steps of:

connecting first and second switching devices in series in a half-bridge arrangement;

providing first and second drivers for said first and second switching devices, respectively;

connecting an inductor at one end to a connection point between said first and second switching devices and at the other end of said inductor providing an output voltage to said load;

connecting a feedback circuit to said load for providing a feedback voltage representative of output current in said load;

providing a pair of parallel comparators, both being connected to both of said first and second drivers through a logic network, thereby providing hysteretic control of said drivers such that said output voltage to said load and thereby said load current is maintained between upper and lower limits;

feeding back said feedback voltage to one of said comparators for establishing said upper limit of said output voltage; and

connecting a reference voltage circuit to both of said comparators for establishing said lower limit of said output voltage.

15. The method of claim 14, wherein said load comprises at least one LED.

16. The method of claim 14, wherein said reference voltage circuit is a bandgap voltage reference circuit.

17. The method of claim 14, further comprising the step of providing an enable circuit connected to one of said comparators for receiving an enable signal, said enable circuit being operable for setting said output voltage at a selected value.

18. The method of claim 17, further comprising the step of regulating the duty cycle of said output voltage by regulating said enable signal to said enable circuit.

19. The method of claim 18, wherein said load comprises at least one LED, and said regulating step includes the step of dimming said at least one LED.

20. The method of claim 18, wherein said load comprises at least one LED, and said regulating step includes the step of switching said Led at high speed to produce an animation effect.

21. The method of claim 17, further comprising the step of clamping said output voltage at a selected value by providing said enable signal to said enable circuit.

22. The method of claim 17, further comprising the step of detecting an open circuit at said load by receiving said output voltage and, when said output voltage exceeds a predetermined value, supplying a clamping signal to said enable circuit.

23. The method of claim 22, wherein said output voltage is received by an open circuit detecting circuit comprising a voltage divider, and a Zener diode connected to said enable circuit, wherein said Zener diode conducts in response to a selected output voltage of said voltage divider, thereby supplying said clamping signal.

24. The method of claim 14, further comprising timing said output voltage by a watchdog timer circuit responsive to said output voltage, and, when said output voltage exceeds a predetermined value for a first predetermined time, issuing signals to said first and second drivers for a second predetermined time.

25. The method of claim 14, wherein said enable signal is provided to a single pin of said chip, thereby performing one-pin control of both output duty cycle and output clamping.