Clock selection circuit and digital processing system for reducing glitches

• US 20050225361A1
• Filed: 04/01/2005
• Published: 10/13/2005
• Est. Priority Date: 04/12/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Rhee, Young-chul
• Granted Patent: US 7,245,168 B2
• Time in Patent Office: Days
• US Class Current: 327/99
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: G06F 1/32 Means for saving power

Abstract

A clock selection circuit and method may operate to generate a clock signal for a digital processing system. In the clock selection circuit, first and second clock control signals may be generated based on a received control signal and/or the inverse of a received clock signal. A first clock signal may be selected when the first clock control signal is activated, and may be output as the selected clock signal. A second clock signal may be selected when the second clock control signal is activated, and may be output as the selected clock signal. The selection operation of the clock selection circuit may reduce the likelihood that a glitch occurs and/or may reduce the amount of power consumed when compared to a conventional clock selection circuit.

Claims

1. A clock selection circuit that receives first and second clock signals, and selects and outputs one of the clock signals, the clock selection circuit comprising:

a first control circuit that generates a first clock control signal activated for a first specified period, and outputs a first gated clock signal based on a delayed first clock signal during the first specified period in response to at least one of a control signal and a first disable signal;

a second control circuit that generates a second clock control signal activated for a second specified period, and outputs a second gated clock signal based on a delayed second clock signal during the second specified period in response to at least one of the control signal inverted and a second disable signal;

a first disable signal generating circuit that generates the first disable signal by delaying the second clock control signal for a specified cycle duration of the delayed first clock signal;

a second disable signal generating circuit that generates the second disable signal by delaying the first clock control signal for a specified cycle duration of the delayed second clock signal; and

a logic circuit that generates an output clock signal by performing a logic operation on the first and second gated clock signals.

2. The clock selection circuit of claim 1, wherein the first control circuit comprises:

a first clock control circuit that generates the first clock control signal in response to the control signal and the first disable signal, wherein said first clock control signal is activated during the first specified period;

a first delay circuit that delays the first clock signal and outputs the delayed first clock signal; and

a first gating circuit that outputs the delayed first clock signal as the first gated clock signal during the first specified period of the first clock control signal.

3. The clock selection circuit of claim 2, wherein the first clock control circuit comprises:

a NOR gate that receives the control signal, the first disable signal, and the second clock control signal; and

a flip-flop that receives an output signal of the NOR gate and outputs the first clock control signal.

4. The clock selection circuit of claim 2, wherein the first gating circuit comprises a NAND gate that receives the first clock control signal and the delayed first clock signal and outputs the first gated clock signal.

5. The clock selection circuit of claim 1, wherein the second control circuit comprises:

a second clock control circuit that generates the second clock control signal in response to the inverted control signal and the second disable signal, wherein said second clock control signal is activated during the second specified period;

a second delay circuit that delays the second clock signal and outputs the delayed second clock signal; and

a second gating circuit that outputs the delayed second clock signal as the second gated clock signal during the second specified period of the second clock control signal.

6. The clock selection circuit of claim 5, wherein the second clock control circuit comprises:

a NOR gate that receives the inverted control signal, the second disable signal, and the first clock control signal; and

a flip-flop that receives an output signal of the NOR gate and outputs the second clock control signal.

7. The clock selection circuit of claim 5, wherein the second gating circuit comprises a NAND gate that receives the second clock control signal and the delayed second clock signal, and outputs the second gated clock signal.

8. The clock selection circuit of claim 1, wherein the first disable signal generating circuit comprises a plurality of flip-flops connected in series, the flip-flops each having a clock port for receiving the delayed first clock signal as input, wherein the second clock control signal is input to a first flip-flop among the plurality of flip-flops, and the first disable signal is output from a last flip-flop among the plurality of flip-flops.

9. The clock selection circuit of claim 1, wherein the second disable signal generating circuit comprises a plurality of flip-flops connected in series, the flip-flops each having a clock port for receiving the delayed second clock signal as input, the first clock control signal is input to a first flip-flop among the plurality of flip-flops, and the second disable signal is output from a last flip-flop among the plurality of flip-flops.

10. The clock selection circuit of claim 1, wherein the logic circuit comprises a NAND gate that receives the first and second gated clock signals and outputs the output clock signal.

29. The clock selection circuit of claim 1, wherein the first control circuit outputs the first gated clock signal only during the first specified period, and wherein the second control circuit outputs the second gated clock signal only during the second specified period.

11. A clock selection circuit that receives first and second clock signals, and selects and outputs one of the clock signals, the clock selection circuit comprising:

a first clock control circuit that generates a first clock control signal having a first activation section of a specified length, said first clock control signal being generated in response to at least one of a control signal and a first disable signal;

a first delay circuit that delays the first clock signal and outputs a delayed first clock signal;

a first gating circuit that outputs the delayed first clock signal as a first gated clock signal during the first activation section of the first clock control signal;

a second clock control circuit that generates a second clock control signal having a second activation section of a specified length, said second clock control signal being generated in response to at least one of the control signal inverted and a second disable signal;

a second delay circuit that delays the second clock signal and outputs a delayed second clock signal;

a second gating circuit that outputs the delayed second clock signal as a second gated clock signal during the second activation section of the second clock control signal;

a first disable signal generating circuit that generates the first disable signal by delaying the second clock control signal for a specified cycle duration of the delayed first clock signal, said first disable signal being generated in response to the delayed first clock signal;

a second disable signal generating circuit that generates the second disable signal by delaying the first clock control signal for a specified cycle duration of the delayed second clock signal, said second disable signal being generated in response to the delayed second clock signal; and

a logic circuit that generates an output clock signal by performing a logic operation on the first and second gated clock signals.

12. The clock selection circuit of claim 11, wherein the first clock control circuit comprises:

an NOR gate that receives the control signal, the first disable signal, and the second clock control signal; and

a flip-flop that receives an output signal of the NOR gate and outputs the first clock control signal.

13. The clock selection circuit of claim 11, wherein the first gating circuit comprises a NAND gate that receives the first clock control signal and the delayed first clock signal and outputs the first gated clock signal.

14. The clock selection circuit of claim 11, wherein the second clock control circuit comprises:

an NOR gate that receives the inverted control signal, the second disable signal, and the first clock control signal; and

a flip-flop that receives an output signal of the NOR gate and outputs the second clock control signal.

15. The clock selection circuit of claim 11, wherein the second gating circuit comprises a NAND gate that receives the second clock control signal and the delayed second clock signal and outputs the second gated clock signal.

16. The clock selection circuit of claim 11, wherein the first disable signal generating circuit comprises a plurality of flip-flops connected in series, the flip-flops each having a clock port for receiving the delayed first clock signal, wherein the second clock control signal is input to a first flip-flop among the plurality of flip-flops, and the first disable signal is output from a last flip-flop among the plurality of flip-flops.

17. The clock selection circuit of claim 11, wherein the second disable signal generating circuit comprises a plurality of flip-flops connected in series, the flip-flops each having a clock port for receiving the delayed second clock signal, wherein the first clock control signal is input to a first flip-flop among the plurality of flip-flops, and the second disable signal is output from a last flip-flop among the plurality of flip-flops.

18. The clock selection circuit of claim 11, wherein the logic circuit comprises a NAND gate that receives the first and second gated clock signals and outputs the output clock signal.

40. A digital processing system including the clock selection circuit of claim 11.

19. A digital processing system, comprising:

a first clock signal source;

a second clock signal source;

a digital processing circuit operating with at least one of the clock frequencies of said first clock signal source and said second clock signal source; and

a clock selection circuit receiving first and second clock signals from the first and second clock signal sources respectively, selecting one of the clock signals, and outputting the selected clock signal to the digital processing circuit, wherein the clock selection circuit comprises,

a first control circuit that generates a first clock control signal activated for a first specified period, and outputs a first gated clock signal based on a delayed first clock signal during the first specified period in response to at least one of a control signal and a first disable signal;

a second control circuit that generates a second clock control signal activated for a second specified period, and outputs a second gated clock signal based on a delayed second clock signal, during the second specified period in response to at least one of the control signal inverted and a second disable signal;

a first disable signal generating circuit that generates the first disable signal by delaying the second clock control signal for a specified cycle duration of the delayed first clock signal;

a second disable signal generating circuit that generates the second disable signal by delaying the first clock control signal for a specified cycle duration of the delayed second clock signal; and

a logic circuit that generates an output clock signal by performing a logic operation on the first and second gated clock signals.

20. The digital processing system of claim 19, wherein the first control circuit comprises:

a first clock control circuit that generates the first clock control signal in response to the control signal and the first disable signal, wherein said first clock control signal is activated during the first specified period;

a first delay circuit that delays the first clock signal and outputs the delayed first clock signal; and

a first gating circuit that outputs the delayed first clock signal as the first gated clock signal during the first specified period of the first clock control signa.

21. The digital processing system of claim 20, wherein the first clock control circuit comprises:

an NOR gate that receives the control signal, the first disable signal, and the second clock control signal; and

a flip-flop that receives an output signal of the NOR gate and outputs the first clock control signal.

22. The digital processing system of claim 20, wherein the first gating circuit comprises a NAND gate that receives the first clock control signal and the delayed first clock signal and outputs the first gated clock signal.

23. The digital processing system of claim 19, wherein the second control circuit comprises:

a second clock control circuit that generates the second clock control signal in response to the inverted control signal and the second disable signal, wherein said second clock control signal is activated during the second specified period;

a second delay circuit that delays the second clock signal and outputs the delayed second clock signal; and

a second gating circuit that outputs the delayed second clock signal as the second gated clock signal during the second specified period of the second clock control signal.

24. The digital processing system of claim 23, wherein the second clock control circuit comprises:

an NOR gate that receives the inverted control signal, the second disable signal, and the first clock control signal; and

a flip-flop that receives an output signal of the NOR gate and outputs the second clock control signal in response to the second clock signal.

25. The digital processing system of claim 23, wherein the second gating circuit comprises a NAND gate that receives the second clock control signal and the delayed second clock signal, and outputs the second gated clock signal.

26. The digital processing system of claim 19, wherein the first disable signal generating circuit comprises a plurality of flip-flops connected in series, the flip-flops each having a clock port into which the delayed first clock signal is input, the second clock control signal is input to a first flip-flop among the plurality of flip-flops, and the first disable signal is output from a last flip-flop among the plurality of flip-flops.

27. The digital processing system of claim 19, wherein the second disable signal generating circuit comprises a plurality of flip-flops connected in series, the flip-flops each having a clock port into which the delayed second clock signal is input, the first clock control signal is input to a first flip-flop among the plurality of flip-flops, and the second disable signal is output from a last flip-flop among the plurality of flip-flops.

28. The digital processing system of claim 19, wherein the logic circuit comprises a NAND gate that receives the first and second gated clock signals and outputs the output clock signal.

30. The clock selection circuit of claim 19, wherein the first control circuit outputs the first gated clock signal only during the first specified period, and wherein the second control circuit outputs the second gated clock signal only during the second specified period.

31. A clock selection circuit comprising:

a first control circuit that generates a first clock control signal based on a control signal and at least one of a first disable signal, a first clock signal and a second clock control signal, and wherein said first control circuit generates a first gated clock signal based on the first clock control signal and a delayed first clock signal;

a second control circuit that generates the second clock control signal based on the control signal inverted and at least one of a second disable signal, a second clock signal and the first clock control signal, and wherein said second control circuit generates a second gated clock signal based on the second clock control signal and a delayed second clock signal; and

a logic circuit that generates an output clock signal by performing a logic operation on the first and second gated clock signals.

32. The clock selection circuit of claim 31, wherein said logic circuit includes a NAND gate.

33. The clock selection circuit of claim 31, further comprising:

a first disable signal generating circuit that generates the first disable signal by delaying the second clock control signal for a specified cycle duration of the delayed first clock signal;

a second disable signal generating circuit that generates the second disable signal by delaying the first clock control signal for a specified cycle duration of the delayed second clock signal.

34. A method of selecting and outputting one of a first clock signal and a second clock signal comprising:

generating a first clock control signal based on a control signal and at least one of a first disable signal, the first clock signal and a second clock control signal;

generating a first gated clock signal based on the first clock control signal and a delayed first clock signal;

generating the second clock control signal based on the control signal inverted and at least one of a second disable signal, the second clock signal and the first clock control signal;

generating a second gated clock signal based on the second clock control signal and a delayed second clock signal;

performing a logic operation on the first and second gated clock signals; and

generating an output clock signal based on said logic operation.

35. The method of claim 34, wherein performing said logic operation includes performing a NAND operation.

36. The method of claim 34, further comprising:

generating the first disable signal by delaying the second clock control signal for a specified cycle duration of the delayed first clock signal; and

generating the second disable signal by delaying the first clock control signal for a specified cycle duration of the delayed second clock signal.

38. A clock selection circuit performing the method of claim 34.

39. A digital processing system performing the method of claim 34.

37. A digital processing system, comprising:

a first clock signal source;

a second clock signal source;

a digital processing circuit operating with at least one of said first clock signal source and said second clock signal source; and

a clock selection circuit receiving the first and second clock signals from the first and second clock signal sources, selecting one of said first and second clock signals, and outputting the selected clock signal to the digital processing circuit, wherein said clock selection circuit receives a control signal and generates two gated clock signals based on the control signal and the control signal inverted.