Electronic tampering detection system

• US 20050225445A1
• Filed: 04/25/2005
• Published: 10/13/2005
• Est. Priority Date: 10/25/2002
• Status: Active Grant

• Current Assignee: Intelligent Devices SEZC Inc.
• Original Assignee: Intelligent Devices Inc. (Heico Corporation)
• Inventors: Petersen, Michael, Wilson, Allan
• Granted Patent: US 7,119,684 B2
• Time in Patent Office: Days
• US Class Current: 340/568.200
• CPC Class Codes: B65D 2211/00 Anti-theft means
• CPC Class Codes: B65D 2401/00 Tamper-indicating means relating to aerosol containers B65D83/224
• CPC Class Codes: B65D 5/42 Details of containers or of foldable or erectable container blanks
• CPC Class Codes: B65D 55/028 initial opening or unauthorised access being indicated by the presence or absence of an audible or electrical signal
• CPC Class Codes: G06K 19/073 Special arrangements for circuits, e.g. for protecting identification code in memory protection against unauthorised use of computer memory G06F12/14
• CPC Class Codes: G06K 19/07798 part of the antenna or the integrated circuit being adapted for rupturing or breaking, e.g. record carriers functioning as sealing devices for detecting not-authenticated opening of containers electronic seals G09F3/03
• CPC Class Codes: G08B 13/126 for a housing, e.g. a box, a safe, or a room

Abstract

An electronic tampering detection system is applied to a blank which can be formed into a package through the use of closure tabs which are coated with an electrically conductive adhesive. An electronic chip or CPU is applied to the blank and electrically conductive traces are printed or otherwise formed on the blank to connect the CPU to a first pair of the closure tabs to form an electric circuit. Other traces on the blank connect the first pair of closure tabs to the other closure tabs to form an enlarged circuit. The CPU has procedure memory, data memory, a power source, a clock and communication means associated therewith. If a package is opened accidentally or intentionally before it should be opened by way of the closure tabs the electric circuit is broken and a time stamp from the CPU clock is stored in the data memory for later retrieval. The circuit can be formed as resistances in parallel and an analog to digital converter can be used to provide an appropriate signal to the CPU. The electric circuit can cover a large portion of the blank'"'"'s surface to provide a signal in the event of unauthorized penetration of the formed package.

Claims

1. A system for detecting tampering or unauthorized entry into a package formed from a blank having at least a pair of closure tabs, an inner surface and an outer surface, said system comprising:

electrically conducting adhesive applied to each of said closure tabs;

a programmable chip applied to one of said blank surfaces, said chip including a power source, procedure memory, data memory, clock means, and communication means; and

electrically conducting trace means applied to one of said blank surfaces, one such trace means connecting said chip to the electrically conducting adhesive of one of said pair of closure tabs, and another of such trace means connecting said chip to the electrically conductive adhesive of the other of said pair of closure tabs;

whereby with said blank having been formed into a closed package through adhesive joining together of said closure tabs, any separation of said tabs will break an electrical circuit which includes said trace means, said electrically conducting adhesive, and said chip means, which break will be recorded with a time stamp in said data memory of said chip.

2. The system of claim 1 wherein said blank includes three pairs of closure tabs, each being coated with electrically conductive adhesive, and wherein said trace means includes first trace means connecting said chip to each closure tab of a first pair of closure tabs, second trace means connecting each closure tab of said first pair of closure tabs to a respective closure tab of a second pair of closure tabs, and third trace means connecting each closure tab of said first pair of closure tabs to a respective closure tab of the third pair of closure tabs.

3. The system of claim 1 wherein said blank includes three pairs of closure tabs, each being coated with electrically conductive adhesive, and wherein said trace means includes first trace means connecting said chip to each closure tab of a first pair of closure tabs, second trace means connecting said chip to one closure tab of each of said second and third pairs of closure tabs, and third trace means connecting the other of each of said second and third pairs of closure tabs to said first trace means.

4. The system of claim 1 wherein said trace means are applied to said blank along a path which defines the shortest practical distance between connection points at each end thereof.

5. The system of claim 1 wherein said trace means are applied to said blank along a circuitous path that covers a substantial extent of said blank.

6. The system of claim 1 wherein said procedure memory and/or said data memory is either volatile or non-volatile and is either internal or external to said chip.

7. The system of claim 1 wherein said communication means includes means for communicating data from said data memory with an external receiver via radio frequence (RF), infrared (IR), or via a direct physical connection.

8. The system of claim 1 wherein said trace means are printed onto said blank as an electrically conductive ink.

9. The system of claim 1 wherein said trace means are screen printed onto said blank.

10. The system of claim 1 wherein said trace means are thin conductive wires adhered to said blank.

11. The system of claim 1 wherein said chip includes an analog to digital converter (ADC);

and

said trace means comprises at least two low resistance electrically conducting trace means applied to one of said blank surfaces and connected at one end thereof to said chip, and at least two high resistance electrically conductive trace means applied to said one blank surface, one of such high resistance trace means connecting one of said low resistance trace means to the electrically conducting adhesive of one of said pair of closure tabs, and another of such high resistance trace means connecting the other of said low resistance trace means to the electrically conductive adhesive of the other of said pair of closure tabs.

12. The system of claim 11 wherein said blank includes three pairs of closure tabs, each being coated with electrically conductive adhesive, and wherein said high resistance trace means includes first high resistance trace means connecting said low resistance trace means to respective ones of a first pair of closure tabs, second trace means connecting said low resistance trace means to respective ones of a second pair of closure tabs, and third trace means connecting said low resistance trace means to respective ones of the third pair of closure tabs.

13. The system of claim 11 wherein the resistance of each of said high resistance trace means differs significantly from the resistance of the others of said high resistance trace means.

14. The system of claim 11 wherein said high resistance trace means are applied to said blank along paths which define the shortest practical distance between connection points at each end thereof.

15. The system of claim 11 wherein said high resistance trace means are applied to said blank along circuitous paths that cover a substantial extent of said blank.

25. The system of claim 1 wherein said blank is formed from a plurality of layers sandwiched together and said trace means are applied between one pair of such layers.

28. The system of claim 1 including means connected to said chip for sensing one or more conditions related to temperature, humidity, vibration, orientation, pressure, radiation and light and for recording in said data memory changes in such conditions beyond predetermined thresholds relating thereto.

16-20. -20. (canceled)

21. A system for detecting tampering or unauthorized entry into a package formed from a blank having at least a pair of closure tabs, an inner surface and an outer surface, said system comprising:

electrically conducting adhesive applied to each of said closure tabs;

a programmable chip applied to one of said surfaces, said chip including a power source, procedure memory, data memory, clock means, an analog to digital converter (ADC), and communication means; and

a grid of low resistance electrically conducting trace means applied to one surface of the blank, and high resistance electrically conductive trace means connecting said chip to said grid at two separate points thereon;

whereby with said blank having been formed into a closed package through adhesive joining together of said closure tabs, any separation of said tabs or penetration of said package will break an electrical circuit which includes said trace means, said electrically conducting adhesive, and said chip means, which break will be recorded as a change in system resistance with a time stamp in said data memory of said chip.

22. The system of claim 21 wherein said blank is formed from a continuous roll of blank material to which said grid of low resistance electrically conducting trace means has been applied prior to formation of said blank.

26. The system of claim 21 wherein said blank is formed from a plurality of layers sandwiched together and at least said grid is located between one pair of such layers.

23. A system for detecting tampering or unauthorized entry into a package formed from a blank having at least a pair of closure tabs, an inner surface and an outer surface, said system comprising:

electrically conducting adhesive applied to each of said closure tabs;

a programmable chip applied to one of said surfaces, said chip including a power source, procedure memory, data memory, clock means, an analog to digital converter (ADC), and communication means;

a coating of low resistance electrically conducting trace means applied to one surface of the blank to cover such surface;

and high resistance electrically conductive trace means connecting said chip to said coating at two separate points thereon;

whereby with said blank having been formed into a closed package through adhesive joining together of said closure tabs, any separation of said tabs or penetration of said package will alter an electrical circuit which includes said trace means, said coating, said electrically conducting adhesive, and said chip means, which separation or penetration will be recorded as a change in system resistance with a time stamp in said data memory of said chip.

24. The system of claim 23 wherein said blank is formed from a continuous roll of blank material to which said low resistance electrically conducting coating has been applied prior to formation of said blank.

27. The system of claim 23 wherein said blank is formed from a plurality of layers sandwiched together and said coating is applied to one of said layers such that it is located between one pair of such layers.