Current switching arrangement for D.A.C. reconstruction filtering
First Claim
1. An arrangement for providing a reduced harmonic content output signal that represents a value of a digital input signal, the arrangement comprising:
- plural storage devices configured to sample and store the digital input signal at different respective phases of a clock signal;
plural current steering digital-to-analog converters (DACs) configured to receive respective stored digital signals from respective ones of the plural storage devices, and to provide respective currents that represent the received stored digital signals; and
a combining arrangement configured to combine the currents from respective ones of the plural current steering DACs, so as to provide the reduced harmonic content output signal that represents the value of the digital input signal.
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Abstract
An arrangement provides a reduced harmonic content output signal that represents a value of a digital input signal. The arrangement includes plural storage devices 301 . . . configured to sample and store the digital input signal at different respective phases of a clock signal. The arrangement also has plural current steering digital-to-analog converters (DACs) 311 . . . configured to receive respective stored digital signals from respective ones of the plural storage devices, and to provide respective currents that represent the received stored digital signals. The arrangement also includes a combining arrangement configured to combine the currents from respective ones of the plural current steering DACs, so as to provide the reduced harmonic content output signal that represents the value of the digital input signal.
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Citations
20 Claims
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1. An arrangement for providing a reduced harmonic content output signal that represents a value of a digital input signal, the arrangement comprising:
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plural storage devices configured to sample and store the digital input signal at different respective phases of a clock signal;
plural current steering digital-to-analog converters (DACs) configured to receive respective stored digital signals from respective ones of the plural storage devices, and to provide respective currents that represent the received stored digital signals; and
a combining arrangement configured to combine the currents from respective ones of the plural current steering DACs, so as to provide the reduced harmonic content output signal that represents the value of the digital input signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for providing a reduced harmonic content output signal that represents a value of a digital input signal, the method comprising:
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sampling and storing the digital input signal at plural respective phases of a clock signal;
receiving respective stored digital signals stored in the storing step, and providing respective currents that represent the received stored digital signals; and
combining the currents so as to provide the reduced harmonic content output signal that represents the value of the digital input signal. - View Dependent Claims (18, 19, 20)
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Specification