Method and apparatus for obtaining power computation parameters

• US 20050225469A1
• Filed: 03/18/2005
• Published: 10/13/2005
• Est. Priority Date: 08/19/2002
• Status: Active Grant

• Current Assignee: Silergy Semiconductor (Samoa) Ltd. (Silergy Corporation)
• Original Assignee: TDK Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: White, Bert
• Granted Patent: US 7,102,556 B2
• Time in Patent Office: Days
• US Class Current: 341/155
• CPC Class Codes: G01R 21/133 by using digital technique

Abstract

A method and apparatus for obtaining power computation parameters is presented. Accurate computation of power requires multiplying voltage and current at the same instant of time and integrating the results over time. The present invention provides a method of using a single Analog to Digital Converter to convert both voltage and current for all the phases of any electrical system and then digitally compensating for the phase error caused by the non-simultaneous sampling of the current and voltage signals. The compensating filter could be implemented as a simple interpolator, an all-pass filter, or a combination of both. A single multiplexer is used to select which signal is processed by the Analog to Digital Converter. By scheduling and converting the voltage and analog signals one at a time, potential for crosstalk is significantly reduced, power requirement is reduced, and die size requirement is reduced.

Claims

1. A method for obtaining power computation parameters comprising:

generating a first digital signal from a plurality of analog signals;

converting said first digital signal to a plurality of second digital signals, wherein each one of said plurality of second digital signals represents a digital form of one of said plurality of analog signals; and

compensating said plurality of second digital signals for differences in sample interval thereby providing digital equivalents of said plurality of analog signals at the same sample time.

2. The method of claim 1, wherein said generating said first digital signal comprises:

multiplexing said plurality of analog signals using a first clock signal to generate a single analog signal; and

converting said single analog signal to said first digital signal using a second clock signal.

3. The method of claim 1, wherein each of said plurality of analog signals comprises a phase of a plurality of multi-phase analog signals.

4. The method of claim 1, wherein said compensating said plurality of second digital signals comprises passing an appropriate one of said plurality of second digital signals through an interpolation filter.

5. The method of claim 1, wherein said compensating said plurality of second digital signals comprises applying a high order interpolation circuit to appropriate ones of said plurality of second digital signals.

6. The method of claim 1, wherein said compensating said plurality of second digital signals comprises passing appropriate ones of said plurality of second digital signals through an allpass filter.

7. The method of claim 1, wherein said converting said single analog signal comprises using oversampling techniques to convert said analog signal to said digital representation.

8. The method of claim 2, wherein said first clock signal is an integer multiple of said second clock signal.

9. The method of claim 1, wherein said plurality of second digital signals comprises power computation parameters.

10. A method for computing power comprising:

selecting a first analog signal from a plurality of analog signals comprising current signals and voltage signals, wherein said selection is at a first sample interval;

converting said first analog signal to a first digital representation using an analog to digital converter at a second sample interval;

obtaining a digital signal for each of said plurality of analog signals from said first digital representation using said first sample interval;

computing electrical power consumption using one of said digital signal representing a current signal and one of said digital signal representing a voltage signal.

11. The method of claim 10, wherein said obtaining a digital signal for each of said plurality of analog signals comprises using a subsequent sample, a current sample, and a previous sample for each of said digital representation of each of said plurality of analog signals in an interpolation filter to generate said digital signal.

12. The method of claim 10, wherein said obtaining a digital signal for each of said plurality of analog signals comprises using a plurality of samples of said digital representation of each of said plurality of analog signals in a high order polynomial interpolator.

13. The method of claim 10, wherein said obtaining a digital signal for each of said plurality of analog signals comprises passing said digital representation of each of said plurality of analog signals through an allpass filter.

14. An apparatus for obtaining power computation parameters comprising:

a first circuit for generating a first digital signal from a plurality of analog signals;

a second circuit for converting said first digital signal to a plurality of second digital signals, wherein each one of said plurality of second digital signals represents a digital form of one of said plurality of analog signals; and

a third circuit for compensating said plurality of second digital signals for differences in sample interval thereby providing digital equivalents of said plurality of analog signals at the same sample time.

15. The apparatus of claim 14, wherein said first circuit comprises:

a multiplexer using a first clock signal to generate a single analog signal from a plurality of multi-phase analog signals; and

an analog to digital converter using a second clock signal to convert said single analog signal to said first digital signal.

16. The apparatus of claim 14, wherein said second circuit comprises:

a demultiplexer using said first clock signal to generate said plurality of second digital signals.

17. The apparatus of claim 15, wherein said third circuit comprises:

a processing unit; and

a phase correction module in said processing unit to compensate said second plurality of digital signals for sample skew associated with conversion in said analog to digital converter.

18. The apparatus of claim 17, wherein said phase correction module is an interpolation filter.

19. The apparatus of claim 17, wherein said phase corretion module is a high order interpolation circuit.

20. The apparatus of claim 17, wherein said phase correction module is an allpass filter.

21. The apparatus of claim 15, wherein said analog to digital converter uses oversampling techniques to convert said analog signal to said first digital signal.

22. The apparatus of claim 15, wherein said analog to digital converter is a delta-sigma converter.

23. The apparatus of claim 15, wherein said first clock signal is an integer multiple of said second clock signal.

24. The apparatus of claim 14, wherein said plurality of analog signals comprises one or more pairs of current and voltage signals.

25. The apparatus of claim 24, wherein each of said one or more pairs of current and voltage signals corresponds to one phase of an analog power signal.