Multilayer circuit board, process of manufacturing same, board for multilayer circuitry, and electronic apparatus

• US 20050225956A1
• Filed: 06/02/2005
• Published: 10/13/2005
• Est. Priority Date: 05/27/2002
• Status: Abandoned Application

• Current Assignee: Haruo Akahoshi, Shingo Kumamoto, Tokihito Suwa
• Original Assignee: Haruo Akahoshi, Shingo Kumamoto, Tokihito Suwa
• Inventors: Akahoshi, Haruo, Suwa, Tokihito, Kumamoto, Shingo
• Application Number:
  US11/142,398
• Publication Number:
  US 20050225956A1
• Time in Patent Office: Days
• US Class Current: 361/795
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 2201/0338 Layered conductor, e.g. layered metal substrate, layered finish layer, layered thin film adhesion layer etched tri-metal structure H05K2201/0361
• CPC Class Codes: H05K 2201/068 wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/093 Layout of power planes, ground planes or power supply conductors, e.g. having special clearance holes therein reduction of cross-talk, noise or interference by patterned shielding planes, ground planes or power planes H05K1/0224
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09554 Via connected to metal substrate
• CPC Class Codes: H05K 2201/09627 Special connections between adjacent vias, not for grounding vias redundant conductors or connections H05K2201/0979
• CPC Class Codes: H05K 2201/09663 Divided layout, i.e. conductors divided in two or more parts branched layout H05K2201/09254
• CPC Class Codes: H05K 3/44 Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits H05K3/0058, H05K3/4608, and H05K3/4641 take precedence
• CPC Class Codes: H05K 3/4641 having integrally laminated metal sheets or special power cores

Abstract

A multilayer circuit board including a laminate of at least one insulating layer and at least one wiring layer. The wiring layer is formed by a composite member having a first metal layer and a second metal layer formed on one or both sides of the first metal layer. The first metal layer having a smaller coefficient of thermal expansion than the second metal layer. The second metal layer having a higher electric conductivity than the first metal layer. The insulating layer has a blind via-hole with a bottom provided by a surface of the second metal layer. A layer-to-layer interconnection portion is provided on the surface of the insulating layer and in the blind via-hole and is formed in the blind via-hole to be in contact with the surface of the second metal layer.

Claims

1. A process of manufacturing a multilayer circuit board in which at least one insulating layer and at least one wiring layer are laminated, the process comprising the steps of:

forming a wiring on the wiring layer in a composite member comprising the wiring layer and the insulating layer integrally formed on the wiring layer, the wiring layer comprising a second metal layer formed on one or both sides of a first metal layer, wherein the second metal layer has a larger coefficient of thermal expansion than the first metal layer;

forming a blind via-hole in the insulating layer such that a bottom portion of the via-hole is formed by a surface of the second metal layer;

forming a layer-to-layer interconnection portion on the surface of the insulating layer and in the blind via-hole in such a manner as to be in contact with the second metal layer surface that forms the blind via-hole bottom portion.

2. A process of manufacturing a multilayer circuit board comprising an insulating layer in which at least one wiring layer is formed, the process comprising the steps of:

forming a wiring on the wiring layer in a composite member comprising the wiring layer and the insulating layer integrally formed on the wiring layer, the wiring layer comprising a second metal layer formed on one or both sides of a first metal layer, wherein the second metal layer has a larger coefficient of thermal expansion than the first metal layer;

forming a blind via-hole in each insulating layer on the opposite surfaces between which the wiring layer is inserted, the blind via-hole having a bottom portion formed by a surface of the second metal substrate; and

forming a layer-to-layer interconnection portion on the surface of the insulating layers and in each blind via-hole in such a manner as to be in contact with the second metal layer surface forming the blind via-hole bottom portion.

3. A process of manufacturing a multilayer circuit board comprising the steps of:

preparing a wiring layer formed by a composite member comprising a first metal layer and a second metal layer formed on one or both sides of the first metal layer, the second metal layer having a higher electric conductivity and a greater coefficient of thermal expansion than the first metal layer;

forming a substrate for multilayer circuitry by laminating the wiring layer on one or both sides of an insulating resin layer;

forming a predetermined wiring on the wiring layer;

covering the wiring formed in the wiring forming step with an insulating layer;

forming a blind via-hole in the insulating layer, or the insulating layer and insulating resin layer, the blind via-hole having a bottom portion formed by a surface of the second metal layer; and

forming a layer-to-layer interconnection portion on the surface of the insulating layer and in the blind via-hole in such a manner as to be in contact with the second metal layer surface in the blind via-hole.

4. A process of manufacturing a multilayer circuit board comprising the steps of:

preparing a wiring layer formed by a composite member comprising a first metal layer and a second metal layer formed on both sides of the first metal layer, the second metal layer having a higher electric conductivity and a greater coefficient of thermal expansion than the first metal layer;

forming a substrate for multilayer circuitry by laminating the wiring layer on both sides of an insulating layer;

forming a predetermined wiring on the wiring layer formed in the wiring preparing step;

covering the wiring formed in the wiring forming step with an insulating layer;

forming a blind via-hole in each insulating layer, or the insulating layer and insulating resin layer on the opposite surfaces between which the insulating layer is inserted, the blind via-hole having a bottom portion formed by a surface of the second metal layer; and

forming a layer-to-layer interconnection portion on the surface of the insulating layer and in the blind via-hole in such a manner as to be in contact with the surface of the second metal layer in each blind via-hole.