Stacked columnar 1T-nMTj MRAM structure and its method of formation and operation

• US 20050226038A1
• Filed: 06/02/2005
• Published: 10/13/2005
• Est. Priority Date: 08/08/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Nejad, Hasan, Seyyedy, Mirmajid
• Granted Patent: US 7,440,339 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

This invention relates to an MRAM array architecture which incorporates certain advantages from both cross-point and 1T-1MTJ architectures during reading operations. The fast read-time and higher signal to noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of MRAM cells each column being provided in a respective stacked memory layer.

Claims

1-33. -33. (canceled)

34. A method of reading a resistive memory device comprising a plurality of stacked layers of resistive memory cells, each layer comprising an array of memory cells arranged in rows and columns, said method comprising:

accessing a selected memory cell by activating a row line coupled to a first side of said selected memory cell and turning on an access transistor which couples a second side of a plurality of memory cells in the same column of said layer, to a sense amplifier.

35. A method as in claim 34, wherein said resistive memory cells are MRAM memory cells.

36. A method as in claim 34 further comprising sensing a resistance value of a selected memory cell with said sense amplifier.

37-61. -61. (canceled)