Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material

• US 20050226067A1
• Filed: 06/08/2005
• Published: 10/13/2005
• Est. Priority Date: 12/19/2002
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Bandyopadhyay, Abhijit, Herner, S. Brad
• Application Number:
  US11/148,530
• Publication Number:
  US 20050226067A1
• Time in Patent Office: Days
• US Class Current: 365/201
• CPC Class Codes: G11C 11/36 using diodes, e.g. as threshold elements , i.e. diodes assuming a stable ON-stage when driven above their threshold (S- or N-characteristic)
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 27/1021 including diodes only

Abstract

A nonvolatile memory cell is described, the memory cell comprising a semiconductor diode. The semiconductor material making up the diode is formed with significant defect density, and allows very low current flow at a typical read voltage. Application of a programming voltage permanently changes the nature of the semiconductor material, resulting in an improved diode. The programmed diode allows much higher current flow, in some embodiments one, two or three orders of magnitude higher, at the same read voltage. The difference in current allows a programmed memory cell to be distinguished from an unprogrammed memory cell. Fabrication techniques to generate an advantageous unprogrammed defect density are described. The memory cell of the present invention can be formed in a monolithic three dimensional memory array, having multiple stacked memory levels formed above a single substrate.

Claims

1. A nonvolatile memory cell comprising:

a first conductor;

a diode comprising amorphous or polycrystalline semiconductor material; and

a second conductor, the semiconductor diode disposed between the first conductor and the second conductor, wherein

before application of a programming voltage the diode has a first maximum barrier height, and

after application of the programming voltage the diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height.

2. The nonvolatile memory cell of claim 1 wherein the semiconductor material is silicon, germanium, or a silicon-germanium alloy.

3. The nonvolatile memory cell of claim 1 wherein the diode is a vertically oriented p-i-n diode.

4. The nonvolatile memory cell of claim 3 wherein the second conductor is above the first conductor, the first conductor extending in a first direction, the second conductor extending in a second direction different from the first direction, the diode vertically disposed between the first and second conductors.

5. The nonvolatile memory cell of claim 1 wherein the programming voltage is between about 3 and about 15 volts.

6. The nonvolatile memory cell of claim 5 wherein the programming voltage is between about 6 and about 9 volts.

7. The nonvolatile memory cell of claim 1 wherein the memory cell resides in a memory array.

8. The nonvolatile memory cell of claim 7 wherein the memory array is a monolithic three dimensional memory array.

9. A nonvolatile memory cell comprising:

a first conductor;

a second conductor; and

a polycrystalline semiconductor junction diode disposed between the first and second conductors,

wherein a data state of the memory cell is determined by a state of an antifuse, and

wherein the polycrystalline semiconductor junction diode is the antifuse.

10. The nonvolatile memory cell of claim 9 wherein the polycrystalline semiconductor junction diode is a vertically oriented p-i-n diode.

11. The nonvolatile memory cell of claim 9 wherein the semiconductor junction diode comprises silicon, germanium, or a silicon-germanium alloy.

12. The nonvolatile memory cell of claim 9 wherein the second conductor is above the first conductor, the diode vertically disposed between the first and second conductors.

13. The nonvolatile memory cell of claim 9 wherein the memory cell is programmed by applying a programming voltage between the first conductor and the second conductor.

14. The nonvolatile memory cell of claim 13 wherein, before programming, upon application of a read voltage, a first current flows between the first conductor and the second conductor, and,

after programming, upon application of the read voltage, a second current flows between the first conductor and the second conductor,

the second current at least an order of magnitude greater than the first current.

15. The nonvolatile memory cell of claim 14 wherein the programming voltage is between about 3 and about 15 volts.

16. The nonvolatile memory cell of claim 15 wherein the programming voltage is between about 6 and about 10 volts.

17. The nonvolatile memory cell of claim 14 wherein the read voltage is between about 0.5 and about 3 volts.

18. The nonvolatile memory cell of claim 17 wherein the read voltage is between about 1 and about 2.5 volts.

19. The nonvolatile memory cell of claim 9 wherein the memory cell resides in a memory array.

20. The nonvolatile memory cell of claim 19 wherein the memory array is a monolithic three dimensional memory array.

21. A method for forming and programming a nonvolatile memory cell, the method comprising:

forming a first conductor;

forming a second conductor;

depositing and doping semiconductor material to form a semiconductor junction diode, the semiconductor junction diode disposed between the first and second conductors;

crystallizing the semiconductor material such that the semiconductor junction diode is polycrystalline,

wherein, during the crystallizing step, the semiconductor material is not in contact with a template material having a lattice mismatch of less than 12 percent with the semiconductor material; and

programming the memory cell by applying a programming voltage between the first and second conductors,

wherein no resistance-switching element having its resistance changed by application of the programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor.

22. The method of claim 21 wherein the semiconductor material is silicon, germanium, or a silicon-germanium alloy.

23. The method of claim 21 wherein the memory cell does not comprise a dielectric antifuse layer.

24. The method of claim 21 wherein the memory cell does not comprise a chalcogenide material.

25. The method of claim 21 wherein, during the crystallization step, the semiconductor material is not in contact with a template material having a lattice mismatch of less than 4 percent with the semiconductor material

26. The method of claim 21 wherein, during the crystallizing step, the semiconductor material is in contact with titanium nitride, tungsten nitride, tantalum nitride, tantalum, tungsten, or titanium tungsten.

27. The method of claim 21 wherein, during the crystallizing step, the semiconductor material is not in contact with titanium suicide, cobalt silicide, or nickel monosilicide.

28. The method of claim 21 wherein, before the programming step, the diode has a first maximum barrier height, and after the programming step, the diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height.

29. A monolithic three dimensional memory array comprising:

a) a first memory level above a substrate, the first memory level comprising;

i) a first plurality of substantially parallel conductors;

ii) a second plurality of substantially parallel conductors above the first conductors;

iii) a first plurality of semiconductor junction diodes, each first diode disposed between one of the first conductors and one of the second conductors; and

iv) a first plurality of one-time-programmable memory cells, each first memory cell adapted to be programmed by application of a programming voltage, each memory cell comprising a portion of one of the first conductors, a portion of one of the second conductors, and one of the first diodes, wherein before programming, each first diode has a first maximum barrier height, and after programming, each first diode has a second maximum barrier height, the second maximum barrier height at least 1.5 times the first maximum barrier height; and

b) a second memory level monolithically formed above the first memory level.

30. The monolithic three dimensional memory array of claim 29 wherein the substrate comprises monocrystalline semiconductor material.

31. The monolithic three dimensional memory array of claim 29 wherein the first diodes comprise silicon, germanium, or a silicon-germanium alloy.

32. The monolithic three dimensional memory array of claim 29 wherein the programming voltage is between about 3 and about 15 volts.

33. The monolithic three dimensional memory array of claim 32 wherein the programming voltage is between about 6 and about 10 volts.

34. The monolithic three dimensional memory array of claim 29 wherein the first diodes are vertically oriented p-i-n diodes.

35. The monolithic three dimensional memory array of claim 29 wherein the second memory level comprises a second plurality of semiconductor junction diodes.

36. A monolithic three dimensional memory array comprising:

a) a first memory level comprising;

i) a plurality of bottom conductors;

ii) a plurality of top conductors; and

iii) a plurality of first polycrystalline semiconductor junction diodes, each diode disposed between one of the bottom and one of the top conductors; and

iv) a first memory cell comprising one of the first diodes, wherein the data state of the first memory cells is determined by the state of an antifuse, and wherein the diode of the first memory cell is the antifuse; and

b) a second memory level monolithically formed above the first memory level.

37. The monolithic three dimensional memory array of claim 36 wherein the semiconductor junction diodes comprise silicon, germanium, or a silicon-germanium alloy.

38. The monolithic three dimensional memory array of claim 36 wherein the bottom conductors are substantially parallel and substantially coplanar and extend in a first direction.

39. The monolithic three dimensional memory array of claim 38 wherein the top conductors are substantially parallel and substantially coplanar and extend in a second direction different from the first direction.

40. The monolithic three dimensional memory array of claim 39 wherein the diodes are vertically oriented p-i-n diodes.

41. The monolithic three dimensional memory array of claim 36 wherein the first memory cell further comprises a portion of one of the bottom conductors and a portion of one of the top conductors, and the first memory cell is programmed by applying a programming voltage between the top conductor and the bottom conductor of the first memory cell.

42. The monolithic three dimensional memory array of claim 41 wherein,

before programming, upon application of a read voltage, a first current flows between the top conductor and the bottom conductor of the first memory cell, and,

after programming, upon application of the read voltage, a second current flows between the top conductor and the bottom conductor of the first memory cell,

the second current at least an order of magnitude greater than the first current.

43. The monolithic three dimensional memory array of claim 42 wherein the programming voltage is between about 3 and about 15 volts.

44. The monolithic three dimensional memory array of claim 43 wherein the programming voltage is between about 6 and about 10 volts.

45. The monolithic three dimensional memory array of claim 42 wherein the read voltage is between about 0.5 and about 3 volts.

46. The monolithic three dimensional memory array of claim 45 wherein the read voltage is between about 1 and about 2.5 volts.

47. A nonvolatile memory cell comprising:

a first conductor;

a diode comprising amorphous or polycrystalline semiconductor material; and

a second conductor, the semiconductor diode disposed between the first conductor and the second conductor, wherein

before application of a programming voltage the diode has a first rectification ratio at a read voltage between about 0.5 and about 2.5 volts, and

after application of the programming voltage the diode has a second rectification ratio at the read voltage, the second rectification ratio at least 10 times the first rectification ratio.

48. The nonvolatile memory cell of claim 47 wherein the second rectification ratio is at least 100 times the first rectification ratio.

49. The nonvolatile memory cell of claim 48 wherein semiconductor material is silicon, germanium, a silicon-germanium alloy, or a semiconductor alloy comprising silicon or germanium.

50. The nonvolatile memory cell of claim 47 wherein the semiconductor material is silicon and the read voltage is between about 1.5 volts and about 2.5 volts.

51. The nonvolatile memory cell of claim 50 wherein the read voltage is about 2 volts.

52. The nonvolatile memory cell of claim 47 wherein the semiconductor material is germanium and the read voltage is between about 0.5 volts and about 2.0 volts.

53. The nonvolatile memory cell of claim 52 wherein the read voltage is about 1.2 volts.

54. The nonvolatile memory cell of claim 47 wherein the semiconductor material is an alloy comprising silicon and germanium.

55. The nonvolatile memory cell of claim 54 wherein the read voltage is between about 1.2 volts and about 2.0 volts.

56. The nonvolatile memory cell of claim 47 wherein the diode is a vertically oriented p-i-n diode.

57. The nonvolatile memory cell of claim 56 wherein the second conductor is above the first conductor, the first conductor extending in a first direction, the second conductor extending in a second direction different from the first direction, the diode vertically disposed between the first and second conductors.

58. The nonvolatile memory cell of claim 47 wherein the programming voltage is between about 3 and about 15 volts.

59. The nonvolatile memory cell of claim 58 wherein the programming voltage is between about 6 and about 9 volts.

60. The nonvolatile memory cell of claim 47 wherein the memory cell resides in a memory array.

61. The nonvolatile memory cell of claim 60 wherein the memory array is a monolithic three dimensional memory array.