MULTI-LAYERED MEMORY CELL STRUCTURE
First Claim
1. A multi-layered memory device for storing data and subsequently reading out the stored data, said memory device utilizing a plurality of existing process conductor layers, said memory device comprising:
- (a) plurality of memory cells arranged in columns and rows, each memory cell including at least one transistor, each transistor being adapted to store information;
(b) plurality of wordlines corresponding to the plurality of rows, each wordline being used in common in each row of said memory cells, at least one of said wordlines being connected to a corresponding memory cell in the column of memory cells;
(c) plurality of bitlines, said bitlines arranged substantially orthogonal to said wordlines, at least one of said bitlines being used in common for data read-out along a column of memory cells;
(d) at least one via-stack, said via-stack comprising a plurality of vias positioned to connect adjacent conduction layers, said via-stack being arranged in close proximity to at least one memory cell, said via-stack being adapted to electrically connect at least one transistor within at least one memory cell to at least one of the existing process conductor layers;
wherein said existing stacked process conductor layers are used to implement within the multi-layered memory device, at least one of an additional wordline as defined in (b) and an additional bitline as defined in (c).
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Abstract
A high-density memory device and design method that utilizes some or all of the existing stacked process conductor layers provided by a manufacturing process to enhance the number of available bitlines and/or wordlines within the memory device. The memory device includes a plurality of memory cells arranged in columns and rows, a plurality of wordlines, a plurality of bitlines, at least one via-stack, wherein said existing stacked process conductor layers are used to implement at least one additional wordline or bitline. The via-stacks consist of a plurality of vias, are located close to a memory cell, and adapted to electrically connect the memory cell to multiple bitlines or multiple wordlines or both0. This design method increases the number of possible connections to or from each individual memory cell. When this design method is combined with varied configurations of basic underlying ROM cell types, even further increased cell density can be achieved.
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Citations
36 Claims
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1. A multi-layered memory device for storing data and subsequently reading out the stored data, said memory device utilizing a plurality of existing process conductor layers, said memory device comprising:
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(a) plurality of memory cells arranged in columns and rows, each memory cell including at least one transistor, each transistor being adapted to store information;
(b) plurality of wordlines corresponding to the plurality of rows, each wordline being used in common in each row of said memory cells, at least one of said wordlines being connected to a corresponding memory cell in the column of memory cells;
(c) plurality of bitlines, said bitlines arranged substantially orthogonal to said wordlines, at least one of said bitlines being used in common for data read-out along a column of memory cells;
(d) at least one via-stack, said via-stack comprising a plurality of vias positioned to connect adjacent conduction layers, said via-stack being arranged in close proximity to at least one memory cell, said via-stack being adapted to electrically connect at least one transistor within at least one memory cell to at least one of the existing process conductor layers;
wherein said existing stacked process conductor layers are used to implement within the multi-layered memory device, at least one of an additional wordline as defined in (b) and an additional bitline as defined in (c). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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19. A method of manufacturing a multi-layered memory device for storing data and subsequently reading out the stored data, said method utilizing existing stacked process conductor layers, said method comprising:
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(a) providing and arranging a plurality of memory cells in columns and rows, each memory cell including at least one transistor, each transistor being adapted to store information;
(b) providing a plurality of wordlines corresponding to the plurality of rows, each wordline being used in common in each row of said memory cells, at least one of said wordlines being connected to a corresponding memory cell in the column of memory cells;
(c) providing and arranging a plurality of bitlines substantially orthogonal to said wordlines, at least one of said bitlines being used in common for data read-out along a column of memory cells;
(d) providing a via-stack by positioning a plurality of vias coupling conductive layers, and arranging said via-stack in close proximity to at least one memory cell, said via-stack being adapted to electrically connect at least one transistor within the at least one memory cell to at least one of the existing process conductor layers;
wherein the existing stacked process conductor layers are used to implement within the memory device at least of an additional wordline as defined in (b) and a bitline as defined in (c).
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Specification